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US 6,724,676 B1Granted
Soft error improvement for latches
AssigneeInfineon Technologies AG
InventorsRonny Schneider, Harald Streif
Life of this patent
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Abstract
Embodiments of the present invention generally provide a soft error-resistant latch circuit. The latch circuit generally includes first and second inverters, each formed by at least two transistors. At least one delay element decouples the gate of at least one of the transistors of one of the inverters from a diffusion area of at least one of the transistors of the other inverter.
Claims27
A latch circuit, comprising:
- first and second inverters, each formed of at least two transistors;
- and
- at least one delay element decoupling a diffusion area of at least one of the transistors of the first inverter from a gate of at least one of the transistors of the second inverter, wherein the delay element comprises a deep trench capacitor.
A latch circuit, comprising:
- first and second inverters, each formed of at least two transistors;
- and
- at least one delay element decoupling a diffusion area of at least one of the transistors of the first inverter from a gate of at least one of the transistors of the second inverter, wherein the delay element comprises at least one track of gate contact material.
A fuse latch having a first node and a second node, comprising:
- a forward inverter having an input node for receiving a signal applied to the first node of the fuse latch and an output node for generating a signal applied to the second node of the fuse latch;
- a feedback inverter having an input node for receiving the signal generated by the forward inverter and an output node;
- a first delay element to decouple the output node of the forward inverter from the input node of the feedback inverter;
- and
- a second delay element to decouple the output node of the feedback inverter from the input node of the forward inverter, wherein the first and second delay elements each comprise at least one deep trench capacitor.
2 more elements
A fuse latch having a first node and a second node, comprising:
- a forward inverter having an input node for receiving a signal applied to the first node of the fuse latch and an output node for generating a signal applied to the second node of the fuse latch;
- a feedback inverter having an input node for receiving the signal generated by the forward inverter and an output node;
- a first delay element to decouple the output node of the forward inverter from the input node of the feedback inverter;
- and
- a second delay element to decouple the output node of the feedback inverter from the input node of the forward inverter, wherein the first and second delay elements each comprise at least one track of gate contact material.
2 more elements
A dynamic random access memory (DRAM) device, comprising:
- a plurality of fuses;
- and
- a plurality of fuse latches to store information about the state of the fuses, each fuse latch comprising a forward inverter having an input node for receiving a signal indicative of the state of one of the fuses, a feedback inverter having an input node for receiving a signal generated by the forward inverter, a first delay element to decouple an output node of the forward inverter from the input node of the feedback inverter, and a second delay element to decouple an output node of the feedback inverter from the input node of the forward inverter, wherein the first and second delay elements each comprise a capacitor.
A dynamic random access memory (DRAM) device, comprising:
- a plurality of memory cells, each comprising a capacitor;
- a plurality of fuses;
- and
- a plurality of fuse latches to store information about the state of the fuses, each fuse latch comprising a forward inverter having an input node for receiving a signal indicative of the state of one of the fuses, a feedback inverter having an input node for receiving a signal generated by the forward inverter, a first delay element to decouple an output node of the forward inverter from the input node of the feedback inverter, and a second delay element to decouple an output node of the feedback inverter from the input node of the forward inverter, wherein the first and second delay elements each comprise a capacitor and wherein the capacitors of the first and second delay elements and the capacitors of the memory cells are each the same type of capacitor.
1 more element
A dynamic random access memory (DRAM) device, comprising:
- a plurality of fuses;
- and
- a plurality of fuse latches to store information about the state of the fuses, each fuse latch comprising a forward inverter having an input node for receiving a signal indicative of the state of one of the fuses, a feedback inverter having an input node for receiving a signal generated by the forward inverter, a first delay element to decouple an output node of the forward inverter from the input node of the feedback inverter, and a second delay element to decouple an output node of the feedback inverter from the input node of the forward inverter, wherein each delay element comprises a track of gate contact material.
Dependencies are inferred from the claim text.