Nonvolatile semiconductor memory device and method for testing the same
AssigneeOki Electric Industry Co., Ltd.
InventorNaotaka Yumoto
Life of this patent
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Abstract
A nonvolatile semiconductor memory device and a method for testing the same by which the faulty memory device causing the unexpected data rewrite can be surely excluded. The test is carried out to judge whether or not a memory element storing a binary information corresponding to presence or not of an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated therefrom, the semiconductor substrate including a source and a drain formed thereon, can exactly hold the electric charge injected to the floating gate in advance. In the test, an approximately equal voltage is applied to the source and drain as the voltage for drawing out the electric charge held in the floating gate.
Claims22
A nonvolatile semiconductor memory device comprising:
- a plurality of memory elements each of which stores a binary information corresponding to an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated from said semiconductor substrate, and each of which including a source and a drain formed on said semiconductor substrate;
- and
- a power source unit applying an approximately same voltage to said sources and said drains in a test mode operation for judging whether the electric charge injected into said floating gates in advance can be held or not,
- wherein said power source unit includes a power source applying a predetermined voltage to said drains in the test mode operation, and a switching element inserted between said power source and said sources, in order to apply a predetermined same voltage to said sources and said drains by using said power source as a common power source in the test mode operation,
- wherein a plurality of bit lines are each electrically connected to respective ones of said plurality of memory elements and said switching element, and
- wherein said switching element is formed of an element having a same structure as an element forming said memory elements.
A nonvolatile semiconductor memory device comprising:
- a plurality of memory elements each of which stores a binary information corresponding to an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated from said semiconductor substrate, and each of which including a source and a drain formed on said semiconductor substrate;
- and
- a power source unit applying an approximately same voltage to said sources and said drains in a test mode operation for judging whether the electric charge injected into said floating gates in advance can be held or not,
- wherein said power source unit includes a power source applying a predetermined voltage to said drains in the test mode operation, and a switching element inserted between said power source and said sources, in order to apply a predetermined same voltage to said sources and said drains by using said power source as a common power source in the test mode operation,
- wherein said power source comprises a regulator capable of applying a predetermined voltage to said drain according to various operational modes including a data read mode, a data write mode, and the test mode operation, and
- wherein during the test mode operation, the predetermined voltage of said regulator is applied to said sources through a latch that temporarily holds data written to said memory elements during the data write mode.
A nonvolatile semiconductor memory device comprising:
- a plurality of memory elements each of which stores a binary information corresponding to an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated from said semiconductor substrate, and each of which including a source and a drain formed on said semiconductor substrate;
- and
- a power source unit applying an approximately same voltage to said sources and said drains in a test mode operation for judging whether the electric charge injected into said floating gates in advance can be held or not,
- wherein said power source unit includes a power source applying a predetermined voltage to said drains in the test mode operation, and a switching element inserted between said power source and said sources, in order to apply a predetermined same voltage to said sources and said drains by using said power source as a common power source in the test mode operation, and
- wherein a plurality of bit lines are each electrically connected to respective ones of said plurality of memory elements, and said plurality of bit lines are connectable with said power source via said switching element which is a single switch.
A nonvolatile semiconductor memory device comprising:
- a plurality of memory elements each of which stores a binary information corresponding to an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated from said semiconductor substrate, and each of which including a source and a drain formed on said semiconductor substrate;
- and
- a power source unit applying an approximately same voltage to said sources and said drains in a test mode operation for judging whether the electric charge injected into said floating gates in advance can be held or not,
- wherein said power source unit applies a voltage of 4.5V equally to said sources and said drains during the test mode operation.
A method for testing a nonvolatile semiconductor memory device for judging whether or not a memory element can hold electric charge injected in advance into a floating gate of said memory element, said memory element storing a binary information corresponding to whether or not the electric charge has been injected into said floating gate which is arranged on a semiconductor substrate so as to be electrically isolated from said semiconductor substrate, said semiconductor substrate including a source and a drain formed thereon,
- the method for testing comprising applying an approximately equal voltage to the source and the drain as a test voltage for drawing out the electric charge held by the floating gate,
- wherein a voltage of 4.5V is applied to said source and said drain as the test voltage.
A nonvolatile memory device comprising:
- a plurality of floating gate type memory cell transistors formed on a semiconductor substrate, each of the cell transistors having a source, a drain and a control gate;
- a plurality of word lines connected to the control gates of the cell transistors;
- a plurality of bit lines connected to the sources of the cell transistors;
- a select line connected to the drains of the cell transistors;
- a test mode circuit that outputs a test mode signal;
- a regulator connected to the test mode circuit, that provides a first voltage to the select line in response to the test mode signal;
- and
- a switching circuit that connects the select line with the bit lines in response to the test mode signal,
- wherein the switching circuit includes a plurality of switching transistors each of which is connected between the select line and one of the bit lines, and
- wherein the switching transistors are floating gate type transistors.
A nonvolatile semiconductor memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a selection line;
- a plurality of floating gate type memory cell transistors, wherein each memory cell transistor has a control gate connected to one of the word lines, a source connected to one of the bit lines, and a drain connected to the selection line;
- a regulator which supplies the selection line with a voltage responsive to a test signal;
- a data latch circuit which holds the voltage supplied by the regulator;
- and
- a plurality of selection transistors which electrically connect the bit lines and the data latch circuit.
Dependencies are inferred from the claim text.