Memory device and method for selectable sub-array activation
AssigneeMatrix Semiconductor, Inc.
InventorsRoy E. Scheuerlein, Bendik Kleveland
Life of this patent
Estimating the term…
Abstract
A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
Claims11
A memory device comprising:
- a memory array comprising a plurality of groups of sub-arrays;
- a register;
- and
- circuitry operative to simultaneously write data into N number of groups of sub-arrays, wherein N is a value stored in the register.
Dependencies are inferred from the claim text.