Erase block architecture for non-volatile memory
AssigneeMicron Technology, Inc.
InventorsFrankie Fariborz Roohparvar, Kevin C. Widmer
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Abstract
A flash memory has erase blocks aligned primarily with array rows and secondarily with array rows. This architecture allows data to be stored across numerous pages without risking accidental erasure caused by crossing multiple erase blocks. As a result, non-volatile memory devices to be more easily substituted for volatile memory devices. In one embodiment, a flash memory includes an array of memory cells that have a plurality of adjacent pages. Addresses of the memory cells are scrambled within the pages to define erase blocks that cross the page boundaries.
Claims23
A flash memory device comprising:
- an array of memory cells arranged in rows and columns;
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array;
- and
- addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
A flash memory comprising:
- an array of memory cells arranged in rows and columns;
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array;
- and
- erase circuitry to erase blocks of the array, wherein the blocks are aligned with the memory array rows such that they cross the plurality of pages.
A processing system comprising:
- a processor;
- and
- a non-volatile memory coupled to communicate with the processor, the non-volatile memory comprises:
- an array of floating gate memory cells arranged in a plurality of addressable banks containing addressable blocks of memory cells;
- a plurality of erase blocks spanning multiple ones of the plurality of addressable banks;
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array;
- and
- addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
A non-volatile memory device, comprising:
- an array of floating gate memory cells arranged in rows and columns and having a plurality of addressable banks containing addressable blocks of memory cells;
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array;
- and
- addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
A non-volatile memory device, comprising:
- an array of floating gate memory cells arranged in a plurality of addressable banks containing addressable blocks of memory cells;
- a plurality of erase blocks spanning multiple ones of the plurality of addressable banks;
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array;
- and
- addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
A method of arranging an erase block architecture for a non-volatile memory, comprising:
- providing a plurality of addressable banks of memory cells in an array;
- providing a plurality of erase blocks, each erase block spanning at least two of the plurality of addressable banks.
A method of erasing in a non-volatile memory, comprising:
- defining erase blocks that span a plurality of pages within a memory array;
- erasing portions of each of a plurality of pages within a memory array without data loss.
Dependencies are inferred from the claim text.