# US 6,724,662 B2 · Method of recovering overerased bits in a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,662 B2 - Document ID: US6724662B2 - Status: Granted - Kind: B2 - Application number: 10/235,265 - Filed: 2002-09-04 - Published: 2004-03-18 - Granted: 2004-04-20 - Earliest claimed: 2002-09-04 - Assignees: Atmel Corporation - Inventors: Danut I. Manea - Web page: https://patentgrep.com/patent/US6724662B2 ## CPC - G11C 16/344: {Arrangements for verifying correct erasure or for detecting overerased cells} - G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method of recovering overerased bits in a memory cell. In the method, a pair of reference currents are internally generated to define a current window corresponding to the erased state of the memory cell. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in a memory array are in an overerased state by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed until the cells are in the erased state. ## Claims ### Claim 1 A method of recovering overerased bits in a memory device following an erase operation, said method comprising: generating a first reference current in the memory device, said first reference current defining a highest current of a current window corresponding to a first reference level defining a state in which a memory cell is in an erased state, determining from a plurality of memory cells a first group of memory cells that have an amount of charge on its floating gate corresponding to a conduction current that is greater than the first reference current, said first group of memory cells being in an overerased state; and applying a plurality of programming pulses to each of the first group of memory cells to place an amount of charge on the floating gate of said cell until the conduction current is less than the first reference current, such that each of the first group of memory cells is programmed from the overerased state to the erased state. ### Claim 2 (depends on 1) The method of claim 1 further comprising: applying a plurality of verify pulses to the specified memory cell, each one of said verify pulses being applied after each one of said programming pulses in an alternating manner. ### Claim 3 (depends on 1) The method of claim 1 wherein said programming pulses increase incrementally in voltage to increase the amount of charge on the floating gate at a steady rate. ### Claim 4 (depends on 1) The method of claim 1 further comprising: generating a second reference current in the memory device, said second reference current defining a lowest current of a current window corresponding to the first reference level defining the state in which a memory cell is in the erased state. ### Claim 5 (depends on 1) The method of claim 1 wherein the memory cell has two memory states per cell. ### Claim 6 (depends on 1) The method of claim 1 wherein the memory cell has four memory states per cell. ### Claim 7 (depends on 1) The method of claim 1 wherein the memory cell is a multi-level memory cell. ### Claim 8 (depends on 1) The method of claim 1 wherein the step of determining the first group includes reading the plurality of memory of cells and comparing the conduction current of each memory cell read to the first reference current. ### Claim 9 A method of recovering overerased bits in a memory device following an erase operation, said method comprising: generating a first reference current in the memory device, said first reference current defining a highest current of a current window corresponding to a first reference level defining a state in which a memory cell is in an erased state; reading a plurality of memory cells to determine a first group of memory cells that have an amount of charge on its floating gate corresponding to a conduction current that is greater than the first reference current, said first group of memory cells being in an overerased state; applying a plurality of programming pulses to program each of the first group of memory cells to place an amount of charge on the floating gate of said cell until the conduction current is less than the first reference current, such that each of the first group of memory cells is programmed from the overerased state to the erased state; and applying a plurality of verify pulses to the specified memory cell, each one of said verify pulses being applied after each one of said programming pulses in an alternating manner. ### Claim 10 (depends on 9) The method of claim 9 wherein said programming pulses increase incrementally in voltage to increase the amount of charge on the floating gate at a steady rate. ### Claim 11 (depends on 9) The method of claim 9 further comprising: generating a second reference current in the memory device, said second reference current defining a lowest current of a current window corresponding to the first reference level defining the state in which a memory cell is in the erased state. ### Claim 12 A method of recovering overerased bits in a memory device following an erase operation, said method comprising: generating a first reference current and a second reference current in the memory device, said first reference current and said second reference current defining a current window defining a first reference level corresponding to a state in which a memory cell is in an erased state, said first reference current defining a highest current of the current window and said second reference current defining a lowest current of the current window; determining from a plurality of memory cells a first group of memory cells that have an amount of charge on its floating gate corresponding to a conduction current that is greater than the first reference current, said first group of memory cells being in an overerased state; applying a plurality of programming pulses to each of the first group of memory cells to place an amount of charge on the floating gate of said cell, said programming pulses increasing incrementally in voltage to increase the amount of charge on the floating gate at a steady rate until the conduction current is less than the first reference current, such that each of the first group of memory cells is programmed from the overerased state to the erased state; and applying a plurality of verify pulses to the specified memory cell, each one of said verify pulses being applied after each one of said programming pulses in an alternating manner. ### Claim 13 (depends on 12) The method of claim 12 wherein the step of determining the first group includes reading the plurality of memory of cells and comparing the conduction current of each memory cell read to the first reference current. ### Claim 14 (depends on 12) The method of claim 12 wherein the memory cell is a multi-level memory cell. ### Claim 15 (depends on 12) The method of claim 12 wherein the memory cell is a single bit per cell memory device.