Erasing method in non-volatile memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsYong-Kyu Lee, Dong-Jun Kim, Min-Soo Cho, Eui-Youl Ryu, Jin-Ho Kim
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Abstract
A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.
Claims14
A method for performing an erase operation in a non-volatile memory device comprising a bulk region of a first conductive type, spaced first and second impurity diffusion regions of a second conductive type formed in the bulk region, a charge storing layer formed between the first and the second impurity diffusion regions, and a conductive electrode formed on the charge storing layer, the method comprising the steps of:
- applying a bulk voltage to the bulk region for a predetermined erase time;
- applying a gate voltage to the conductive electrode for the predetermined erase time, the gate voltage being greater than or equal to the bulk voltage;
- applying a first voltage to the first impurity diffusion region during the predetermined erase time, wherein the first voltage is greater than the gate voltage;
- applying a second voltage to the second impurity diffusion region during the predetermined erase time, wherein the second voltage is greater than the gate voltage, wherein the first and second voltages are different;
- and
- switching the first and second voltages at least one time during the predetermined erase time such that the first voltage is applied to the second impurity region while the second voltage is applied to the first impurity region.
A method for performing an erase operation in a memory cell comprising a bulk region of a first conductive type, spaced source and drain regions of a second conductive type formed in the bulk region, and a gate electrode formed between the source and drain regions, the method comprising the steps of:
- applying a first voltage to the source region and a second voltage to the drain region for a portion of a predetermined erase time;
- and
- applying the second voltage to the source region and the first voltage to the drain region for a portion of the predetermined erase time.
A method for performing an erase operation in a non-volatile memory device comprising a bulk region of a first conductive type, spaced source and drain regions of a second conductive type formed in the bulk region, and a gate electrode formed between the source and drain regions, the method comprising the steps of:
- applying a first voltage and a second voltage to the source and drain regions, respectively, for a predetermined erase time;
- applying a third voltage to the gate electrode, wherein the potential differences between the third voltage and the first and second voltages are sufficient to generate electric fields between the gate electrode and the source and drain regions to inject holes into the source and drain regions, respectively;
- and
- switching the first voltage to the drain region and the second voltage to the source region at least one time during the predetermined erase time.
Dependencies are inferred from the claim text.