Method and circuit for generating reference voltages for reading a multilevel memory cell

A multilevel memory comprising:

• a memory array made up of a plurality of memory cells;
• a read circuit for reading said memory cells;
• and
• a circuit for generating reference voltages, including a first reference cell and a second reference cell having, respectively, a first reference programming level and a second reference programming level, a first reference circuit and a second reference circuit respectively connected to said first and said second reference cells and having respective output terminals which respectively supply a first reference voltage and a second reference voltage;
• and
• a voltage-dividing circuit having a first connection node and a second connection node respectively connected to said output terminals of said first reference circuit and of said second reference circuit to receive, respectively, said first reference voltage and said second reference voltage, and a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.

A device, comprising:

• first, second and third memory cells, each memory cell configured to be programmed at any one of a plurality of programming levels;
• the first memory cell being programmed at a highest one of the plurality of programming levels;
• the second memory cell being programmed at a lowest one of the plurality of programming levels;
• the third memory cell being programmed at one of the plurality of programming levels;
• a first reference circuit, coupled to the first memory cell and configured to produce a first voltage level at a first reference output, the first voltage level corresponding to the programming level stored in the first memory cell;
• a second reference circuit, coupled to the second memory cell and configured to produce a second voltage level at a second reference output, the second voltage level corresponding to the programming level stored in the second memory cell, the first voltage level and the second voltage level having a voltage difference therebetween;
• a read circuit, coupled to the third memory cell and configured to produce a read voltage level at a read output, the read voltage level corresponding to the programming level stored in the third memory cell;
• a voltage divider circuit having a first input coupled to the first reference output, a second input coupled to the second reference output and a plurality of divider outputs, the voltage divider circuit being configured to divide the voltage difference between the first and second voltage levels into a plurality of divider voltage levels and further configured to couple the first and second voltage levels and each of the plurality of divider voltage levels to a respective one of the divider outputs;
• and
• a converter circuit having a plurality of reference inputs coupled to respective divider outputs, and a read input coupled to the read output and a digital output, the converter circuit being configured to determine to which of the plurality of programming levels the third memory cell is programmed and to provide a corresponding digital signal at the digital output.

A method, comprising:

• producing a read voltage level, corresponding to a programming level stored in a memory cell to be read;
• producing a first voltage level, corresponding to a programming level stored in a first reference cell, the first reference cell having been programmed to a known, highest level of a plurality of programming levels to which the first reference cell or the memory cell may be programmed;
• producing a second voltage level, corresponding to a programming level stored in a second reference cell, the second reference cell having been programmed to a known, lowest level of a plurality of programming levels to which the first or second reference cell or the memory cell may be programmed;
• generating a plurality of additional voltage levels that are intermediate between the first voltage level and the second voltage level and are at equal distances apart;
• comparing the read voltage level to the first and second voltage levels and to the plurality of additional voltage levels;
• and
• outputting a numerical value corresponding to the programming level of the memory cell, as determined in the comparing step.