# US 6,724,655 B2 · Memory cell using negative differential resistance field effect transistors

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- Number: US 6,724,655 B2
- Document ID: US6724655B2
- Status: Granted
- Kind: B2
- Application number: 10/029,077
- Filed: 2001-12-21
- Published: 2002-05-09
- Granted: 2004-04-20
- Earliest claimed: 2000-06-22
- Assignees: Progressant Technologies, Inc.
- Inventors: Tsu-Jae King
- Web page: https://patentgrep.com/patent/US6724655B2

## CPC

- G11C 5/142: {Contactless power supplies, e.g. RF, induction, or IR}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 11/39: using thyristors {or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT}
- G11C 11/41: forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/68: Floating-gate IGFETs
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory cell using both negative differential resistance (NDR) and conventional FETs is disclosed. A pair of NDR FETs are coupled in a latch configuration so that a data value passed by a transfer FET can be stored at a storage node. By exploiting an NDR characteristic, the memory cell can be implemented with fewer active devices. Moreover, an NDR FET can be manufactured using conventional MOS processing steps so that process integration issues are minimized as compared to conventional NDR techniques.

## Claims

### Claim 1

A memory cell comprising:
a transfer field effect transistor (FET), said transfer FET being configured to receive and/or transfer a data value from a data line to a storage node in response to a write and/or read signal respectively provided to the memory cell; and
a first negative differential resistance (NDR) FET, said first NDR FET being configured to receive a first gate bias signal and having a first NDR FET source terminal coupled to said storage node, and a first NDR FET drain terminal coupled to a first voltage potential at a first node; and
a second negative differential resistance (NDR) FET, said second NDR FET being configured to receive a second gate bias signal and having a second NDR FET drain terminal coupled to said storage node, and a second NDR FET drain terminal coupled to a second voltage potential at a second node; and
wherein the memory cell uses said negative differential resistance characteristic of said first NDR FET and said second NDR FET to store said data value at said storage node.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein said first NDR FET and said second NDR FET are connected in series.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein said first bias voltage is coupled to said first voltage potential.

### Claim 4 (depends on 1)

The memory cell of claim 1, wherein said first NDR FET, said second NDR FET and said transfer FET use a common substrate and one or more common layers.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein said first bias voltage and said second bias voltage are approximately equal.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein said first bias voltage is substantially greater than said second bias voltage.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein said first bias voltage and said second bias voltage are generated by a charge pump circuit.

### Claim 8 (depends on 4)

The memory cell of claim 4, wherein said common substrate is a silicon on insulator (SOI) substrate.

### Claim 9 (depends on 1)

The memory cell of claim 1, wherein said storage node includes a source/drain region shared by said transfer FET and at least one of said first NDR FET and/or said second NDR FET.

### Claim 10 (depends on 1)

The memory cell of claim 1, wherein at least one of said first NDR FET and second NDR FET use a charge trapping region that is located at an interface between a gate insulation layer and a substrate.

### Claim 11 (depends on 1)

The memory cell of claim 1, wherein at least one of said first NDR FET and second NDR FET use a charge trapping region that is located within a gate dielectric forming part of a gate insulation layer.

### Claim 12

A method of operating a memory cell having a storage node comprising the steps of:
receiving or transferring a data value from a data line by gating a transfer field effect transistor (FET) in response to a write or read signal; and
biasing a first negative differential resistance capable FET (first NDR FET) with a first bias signal so that said first NDR FET selectively operates with a first negative differential resistance (NDR) characteristic; and
biasing a second negative differential resistance capable FET (second NDR FET) with a second bias signal so that said second NDR FET to operate with a first negative differential resistance (NDR) characteristic; and
coupling said first NDR FET and said second NDR FET in a latched configuration with said transfer FET so that said data value can be read or written to the storage node in cooperation with said transfer FET; and
operating said first NDR FET and said second NDR FET with said first NDR characteristic and said second NDR characteristic so that said data value is stored at said storage node.

### Claim 13 (depends on 12)

The method of claim 12, wherein at least one of said first NDR FET and said second NDR FET do not operate with an NDR characteristic during an initial period of a read or write operation.

### Claim 14 (depends on 13)

The method of claim 13, wherein at least one of said first NDR FET and said second NDR FET operate with an NDR characteristic during a final period of a read or write operation so that said at least one of said first NDR FET and said second NDR FET turns off at the end of said final period.

### Claim 15 (depends on 12)

The method of claim 12, wherein said first bias signal and said second signal are selectively enabled depending on an operation performed by the memory cell.

### Claim 16 (depends on 12)

The method of claim 12, wherein said first bias signal and said second signal differ by an amount equal to a threshold voltage.