Pulsed write techniques for magneto-resistive memories

A magneto-resistive storage device comprising:

• a magneto-resistive bit having a first end and a second end;
• a word line extending adjacent the magneto-resistive bit, the word line coupled to the first end of the magneto-resistive bit;
• a word line current generator adapted to selectively provide a word line current to the word line in response to a control;
• a switch coupled to the second end of the magneto-resistive bit that can selectively provide a path for a read sense current or a write sense current to flow from the word line, through at least part of the magneto-resistive bit, and to a predetermined voltage terminal in response to a control;
• a read circuit coupled to the word line, where the read circuit is configured to selectively provide a path for the read sense current to flow to the word line, the read circuit detecting a resistive state of the magneto-resistive bit via the read sense current in response to a control;
• and
• a controller coupled to the word line current generator, to the switch, and to the read circuit, where the controller is configured to perform a write of the magneto-resistive bit by providing a control to the word line current generator such that the word line current generator provides a word line current to the word line, providing a control to the switch such that the switch provides a path for the write sense current to flow from the word line, through at least part of the magneto-resistive bit, and to the predetermined voltage terminal, and providing a control to the read circuit to such that the read circuit does not provide a path for the read sense current to flow to the word line, and where the controller is further configured to perform a read of the magneto-resistive bit by providing a control to the word line current generator such that the word line current generator does not provide a word line current to the word line, providing a control to the switch such that the switch provides a path for the read sense current to flow from the word line, through at least part of the magneto-resistive bit, and to the predetermined voltage terminal, and providing a control to the read circuit such that the read circuit provides a path for the read sense current to flow to the word line and to read the resistive state of the magneto-resistive bit via the read sense current.

A magneto-resistive storage element comprising:

• a first magneto-resistive bit having a first end and a second end;
• a second magneto-resistive bit having a first end and a second end;
• a word line extending adjacent the first and second magneto-resistive bits such that a word line current passing through the word line provides a magnetic field component toward one end of the first magneto-resistive bit and toward the other end of the second magneto-resistive bit, the word line coupled to the first end of the first magneto-resistive bit and to the first end of the second magneto-resistive bit;
• and
• a switch coupled to the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit for selectively providing a path for a write sense current to flow from the word line, through at least part of the first and second magneto-resistive bits, and to a predetermined voltage terminal.

A magneto-resistive storage device comprising:

• a magneto-resistive bit with a first end and a second end;
• a word line extending adjacent the magneto-resistive bit, where the word line is coupled to the first end of the magneto-resistive bit;
• a controller that is configured to provide a control for at least a write and a read to the magneto-resistive bit;
• a word line current generator coupled to the controller and to the word line, where the word line current generator is configured to provide a word line current to the word line in response to a write indication from the controller and does not provide a word line current to the word line in response to a read indication from the controller;
• a switch coupled to the controller, to the second end of the magneto-resistive bit, and to a predetermined voltage terminal, where the switch is configured to provide a path for the write sense current to flow from the word line, through at least part of the magneto-resistive bit, and to the predetermined voltage terminal in response to a write indication from the controller, and where the switch is further configured to provide a path for the read sense current to flow from the word line, through at least part of the magneto-resistive bit, and to the predetermined voltage terminal in response to a read indication from the controller;
• and
• a read circuit coupled to the controller and to the word line, where the read circuit is configured to not provide a path for the read sense current to flow to the word line in response to a write indication from the controller, and where the read circuit is further configured to provide a path for the read sense current to flow to the word line in response to a read indication from the controller, and where the read circuit is further configured to read the resistive state of the magneto-resistive bit via the read sense current in response to the read indication.

A magneto-resistive memory comprising:

• a latch circuit including a first inverter and a second inverter coupled together in a cross-coupled configuration, each of the first and second inverters having a positive supply terminal, a negative supply terminal, an input terminal and an output terminal, the positive supply terminal of the first and second inverters coupled to a power supply voltage;
• the latch circuit further including a load transistor for loading a state into the latch circuit, the load transistor having a source terminal coupled to the input terminal of the first inverter, a drain terminal coupled to the input terminal of the second inverter, and a gate terminal;
• at least one magneto-resistive memory cell having a first magneto-resistive bit with a first end and a second end, and a second magneto-resistive bit having a first end and a second end, the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit being selectively coupled to ground through one or more switches;
• a first word line coupled to the negative supply terminal of the first inverter and extending adjacent the first magneto-resistive bit of at least one magneto-resistive memory cell, each of the first magneto-resistive bits having a first end coupled to the first word line;
• a second word line coupled to the negative supply terminal of the second inverter and extending adjacent the second magneto-resistive bit of at least one magneto-resistive memory cell, each of the second magneto-resistive bits having a first end coupled to the second word line;
• and
• a write transistor having a source terminal coupled to the first word line, a drain coupled to the second word line, and a gate coupled to a write control terminal, the write transistor for selectively connecting the first word line and the second word line depending on the state of the write control terminal.