Semiconductor device having a load less four transistor cell

A semiconductor device comprising a memory cell array having a plurality of unit memory cells disposed in a row and column array,

• said unit memory cell including:
• first and second field effect transistors of a first conduction type;
• third and fourth field effect transistors of a second conduction type;
• and
• first and second resistance elements,
• said unit memory cell being constructed such that a source/drain path of said first field effect transistor is connected between a first power supply and a first node, a source/drain path of said second field effect transistor is connected between said first power supply and a second node, a gate electrode of said first field effect transistor is connected to said second node, a gate electrode of said second field effect transistor is connected to said first node, a series-connected structure constructed by connecting a source/drain path of said third field effect transistor and said first resistance element in series is connected between said first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of said fourth field effect transistor and said second resistance element in series is connected between said second node and a second bit line paired with said first bit line, and both gate electrodes of said third and fourth field effect transistors are connected to a word line, thereby constituting a load less four transistor cell,
• wherein said first resistance element is formed within a diffusion region constituting an electrode of said third field effect transistor and said second resistance element is formed within a diffusion region constituting an electrode of said fourth field effect transistor.

A semiconductor device comprising a memory cell array having a plurality of unit memory cells disposed in a row and column array,

• said unit memory cell including:
• first and second field effect transistors of a first conduction type;
• third and fourth field effect transistors of a second conduction type;
• and
• first and second resistance elements,
• said unit memory cell being constructed such that a source/drain path of said first field effect transistor is connected between a first power supply and a first node, a source/drain path of said second field effect transistor is connected between said first power supply and a second node, a gate electrode of said first field effect transistor is connected to said second node, a gate electrode of said second field effect transistor is connected to said first node, a series-connected structure constructed by connecting a source/drain path of said third field effect transistor and said first resistance element in series is connected between said first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of said fourth field effect transistor and said second resistance element in series is connected between said second node and a second bit line paired with said first bit line, and both gate electrodes of said third and fourth field effect transistors are connected to a word line, thereby constituting a load less four transistor cell,
• wherein said first conduction type and said second conduction type are opposite one another;
• and
• wherein said first resistance element is connected between said third field effect transistor and said first bit line, and said second resistance element is connected between said fourth field effect transistor and said second bit line.

A semiconductor device comprising a memory cell array having a plurality of unit memory cells disposed in a row and column array,

• said unit memory cell including:
• first and second field effect transistors of a first conduction type;
• third and fourth field effect transistors of a second conduction type;
• and
• first and second resistance elements,
• said unit memory cell being constructed such that a source/drain path of said first field effect transistor is connected between a first power supply and a first node, a source/drain path of said second field effect transistor is connected between said first power supply and a second node, a gate electrode of said first field effect transistor is connected to said second node, a gate electrode of said second field effect transistor is connected to said first node, a series-connected structure constructed by connecting a source/drain path of said third field effect transistor and said first resistance element in series is connected between said first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of said fourth field effect transistor and said second resistance element in series is connected between said second node and a second bit line paired with said first bit line, and both gate electrodes of said third and fourth field effect transistors are connected to a word line, thereby constituting a load less four transistor cell,
• wherein said first conduction type and said second conduction type are opposite one another;
• and
• wherein said first resistance element is formed within a contact hole located in a path connecting said third field effect transistor and said first bit line to each other and connected to said first bit line, and said second resistance element is formed within a contact hole located in a path connecting said fourth field effect transistor and said second bit line to each other and connected to said second bit line.

A semiconductor device comprising a memory cell array having a plurality of unit memory cells disposed in a row and column array,

• said unit memory cell including:
• first and second field effect transistors of a first conduction type;
• third and fourth field effect transistors of a second conduction type;
• and
• first and second resistance elements,
• said unit memory cell being constructed such that a source/drain path of said first field effect transistor is connected between a first power supply and a first node, a source/drain path of said second field effect transistor is connected between said first power supply and a second node, a gate electrode of said first field effect transistor is connected to said second node, a gate electrode of said second field effect transistor is connected to said first node, a series-connected structure constructed by connecting a source/drain path of said third field effect transistor and said first resistance element in series is connected between said first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of said fourth field effect transistor and said second resistance element in series is connected between said second node and a second bit line paired with said first bit line, and both gate electrodes of said third and fourth field effect transistors are connected to a word line, thereby constituting a load less four transistor cell,
• wherein each of said first and second field effect transistors is an n-type field effect transistor, each of said third and fourth field effect transistors is a p-type field effect transistor, and said first power supply is a lower power supply;
• and
• wherein said first resistance element is connected between said third field effect transistor and said first bit line, and said second resistance element is connected between said fourth field effect transistor and said second bit line.

A semiconductor device comprising a memory cell array having a plurality of unit memory cells disposed in a row and column array,

• said unit memory cell including:
• first and second field effect transistors of a first conduction type;
• third and fourth field effect transistors of a second conduction type;
• and
• first and second resistance elements,
• said unit memory cell being constructed such that a source/drain path of said first field effect transistor is connected between a first power supply and a first node, a source/drain path of said second field effect transistor is connected between said first power supply and a second node, a gate electrode of said first field effect transistor is connected to said second node, a gate electrode of said second field effect transistor is connected to said first node, a series-connected structure constructed by connecting a source/drain path of said third field effect transistor and said first resistance element in series is connected between said first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of said fourth field effect transistor and said second resistance element in series is connected between said second node and a second bit line paired with said first bit line, and both gate electrodes of said third and fourth field effect transistors are connected to a word line, thereby constituting a load less four transistor cell,
• wherein each of said first and second field effect transistors is an n-type field effect transistor, each of said third and fourth field effect transistors is a p-type field effect transistor, and said first power supply is a lower power supply;
• and
• wherein said first resistance element is formed within a contact hole located in a path connecting said third field effect transistor and said first bit line to each other and connected to said first bit line, and said second resistance element is formed within a contact hole located in a path connecting said fourth field effect transistor and said second bit line to each other and connected to said second bit line.