Memory cell leakage reduction
AssigneeIntel Corporation
InventorsYibin Ye, Dinesh Somasekhar, Vivek K. De
Life of this patent
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Abstract
Leakage current from non-selected memory cells is substantially eliminated by placing a negative voltage on the selection line of the non-selected cells. This negative voltage on the gate of the access transistors in the cells reduces the leakage current that would otherwise leak onto a shared sense line if the selection line were biased at 0 volts. In one embodiment the pre-charge voltage on the affected sense line is reduced so that the difference between the pre-charge voltage and the negative voltage does not exceed the design voltage of the transistors in the memory cells.
Claims21
An apparatus, comprising:
- first and second memory cells;
- a first sense line coupled to the first and second memory cells;
- a first selection line coupled to the first memory cell and a second selection line coupled to the second memory cell;
- a pre-charge circuit to charge the first sense line to a pre-charge voltage less than a supply voltage;
- and
- control logic to assert a signal on the first selection line responsive to the first memory cell being selected for a read operation and to couple a negative voltage onto the second selection line responsive to the second memory cell not being selected for the read operations;
- wherein a difference between the pre-charge voltage and the negative voltage is no greater than a difference between the supply voltage and a signal ground voltage.
An apparatus, comprising:
- a memory device having memory cells electrically connected in a matrix defined by sense lines and selection lines;
- a pre-charge circuit to place a pre-charge voltage on a particular one of the sense lines;
- control logic to place a first voltage having a first polarity on a particular one of the selection lines to read a particular memory cell and to place a second voltage having a second polarity opposite the first polarity on remaining ones of the selection lines;
- wherein a difference between the first voltage and the second voltage is no greater than a difference between the supply voltage and a signal ground voltage.
A system, comprising:
- a processor;
- a memory controller coupled to the processor;
- a memory coupled to the memory controller and comprising
- a plurality of memory cells;
- a sense line coupled to the plurality of memory cells;
- a first selection line coupled to a first memory cell of the plurality of memory cells;
- a second selection line coupled to a second memory cell of the plurality of memory cells;
- a pre-charge circuit to charge the sense line to a pre-charge voltage;
- and
- control logic to couple the supply voltage onto the first selection line responsive to the first memory cell being selected for a read operation and to reverse-bias the second memory cell responsive to the second memory cell not being selected for the read operations;
- wherein a difference between the pre-charge voltage and a reverse-bias voltage used on the second memory cell is no greater than a difference between the supply voltage and a signal ground voltage.
A method, comprising:
- pre-charging a sense line in a memory;
- placing a positive voltage on a first selection line in the memory to select a first memory cell for a read operation;
- placing a negative voltage on a second selection line in the memory to reverse-bias a second memory cell that is not selected for the read operation;
- and
- reading a stored state from the first memory;
- wherein a difference between the pre-charge voltage and the negative voltage is no greater than a difference between the supply voltage and a signal ground voltage.
Dependencies are inferred from the claim text.