# US 6,724,645 B1 · Method and apparatus for shortening read operations in destructive read memories

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- Number: US 6,724,645 B1
- Document ID: US6724645B1
- Status: Granted
- Kind: B1
- Application number: 10/356,443
- Filed: 2003-01-30
- Granted: 2004-04-20
- Earliest claimed: 2003-01-30
- Assignees: Agilent Technologies, Inc.
- Inventors: Ralph H. Lanham; David Victor Pietromonaco
- Web page: https://patentgrep.com/patent/US6724645B1

## CPC

- G11C 11/22: using ferroelectric elements
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus and method for shortening the read operation (typically the longest operation) in a destructive read memory is disclosed. The rewrite step is separated from the read operation and delayed to the subsequent clock cycle. A FeRAM memory cell having two ports is needed so that consecutive operations do not conflict with each other. A read operation is initiated through a first port in a first clock cycle. In the subsequent clock cycle, the rewrite finishes through the first port. The next operation utilizes the second port, without conflicting with the rewrite process. By alternating ports used in each clock cycle, the rewrite step is hidden in the subsequent clock cycle to shorten the read operation. In an alternate method, all read operations are initiated through one port, while the second port is reserved exclusively for write operations and rewrites.

## Claims

### Claim 1

A memory cell, comprising:
a first and second port;
a ferroelectric capacitor for data storage, having a first and second electrode;
a first switch connecting the first port to the first electrode of the ferroelectric capacitor during a read or write operation;
a second switch connecting the second port to the first electrode of the ferroelectric capacitor during a read or write operation; and
a memory cache coupled to the first and second port that stores the data from a read operations for rewrite back to the ferroelectric capacitor.

### Claim 2 (depends on 1)

A memory cell as in claim 1, wherein a read operation accesses the ferroelectric capacitor through a different port than the port used by the subsequent operation.

### Claim 3 (depends on 1)

A memory cell as in claim 1, wherein the first port is used exclusively to access the ferroelectric capacitor during a read operation, and the second port is used exclusively to access the ferroelectric capacitor during a write operation.

### Claim 4

A method for operating a memory array, comprising:
providing an array of memory cells;
performing a destructive read of data from a memory cell in a first clock cycle without rewriting the data; and
rewriting the data to the memory cell in the subsequent clock cycle.

### Claim 5 (depends on 4)

The method as in claim 4, wherein:
each memory cell is accessible through a first and a second port;
the read operation accesses a memory cell via a first port; and
the rewrite also accesses the memory cell via the first port.

### Claim 6 (depends on 5)

The method as in claim 5, wherein the read operation and the subsequent operation access the memory cells of the array using different ports.

### Claim 7 (depends on 4)

The method as in claim 4, wherein
performing a read operation reads from the memory array exclusively via the first ports;
performing the rewrite accesses the memory array exclusively via the second ports; and
performing a write operation writes to the memory array exclusively via the second ports.

### Claim 8 (depends on 7)

The method as in claim 7, further comprising:
delaying the write operation by one clock cycle.