# US 6,724,601 B2 · ESD protection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,601 B2 - Document ID: US6724601B2 - Status: Granted - Kind: B2 - Application number: 09/811,114 - Filed: 2001-03-16 - Published: 2002-09-19 - Granted: 2004-04-20 - Earliest claimed: 2001-03-16 - Assignees: Integrated Device Technology, Inc. - Inventors: Chuen-Der Lien; Chau-Chin Wu; Ta-Ke Tien - Web page: https://patentgrep.com/patent/US6724601B2 ## CPC - H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An integrated circuit having an electrostatic discharge (ESD) protection circuit, a core protection circuit, a sensitive core circuit and peripheral circuitry is provided. The ESD protection circuit is coupled between the VDD voltage supply terminal and the VSS voltage supply terminal, and is capable of providing protection to the peripheral circuitry. The ESD protection circuitry requires help from core protection circuit to protect the sensitive core circuit. The core protection circuit and the sensitive core circuit are coupled in series between the VDD and VSS voltage supply terminals, with the core protection circuit coupled to the VDD voltage supply terminal. The sensitive core circuit has a VCC voltage supply terminal coupled to receive a VCC supply voltage from the core protection circuit. The core protection circuit is configured to cause the VCC supply voltage to rise slowly with respect to a rising voltage on the VDD voltage supply terminal during power-on of the integrated circuit. The core protection circuit is further configured to disconnect the VCC voltage supply terminal from the VDD voltage supply when a voltage on the VDD voltage supply terminal exceeds the nominal VDD supply voltage by a predetermined amount. ## Claims ### Claim 1 An integrated circuit comprising: a VDD voltage supply terminal; a VSS voltage supply terminal; an electrostatic discharge (ESD) protection circuit coupled between the VDD voltage supply terminal and the VSS voltage supply terminal; a core protection circuit coupled to the VDD voltage supply terminal; and a core circuit coupled between the core protection circuit and the VSS voltage supply terminal, the core circuit having a VCC voltage supply terminal coupled to receive a VCC supply voltage from the core protection circuit, wherein the core protection circuit is configured to cause the VCC supply voltage to rise slowly with respect to a rising voltage on the VDD voltage supply terminal during power-on of the integrated circuit. ### Claim 2 (depends on 1) The integrated circuit of claim 1, further comprising a peripheral circuit coupled between the VDD voltage supply terminal and the VSS voltage supply terminal, wherein the peripheral circuit controls the operation of the core circuit, and wherein the core circuit is more sensitive than the peripheral circuit to ESD events occurring on the VDD voltage supply terminal. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the ESD protection circuit is configured to protect the peripheral circuit during an ESD event, without assistance from the core protection circuit. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the core circuit comprises an array of six-transistor (6-T) static random access memory (SRAM) cells. ### Claim 5 (depends on 4) The integrated circuit of claim 4, wherein the 6-T SRAM cells have a minimum feature size of 0.18 microns or less. ### Claim 6 (depends on 4) The integrated circuit of claim 4, wherein the core protection circuit comprises a p-channel transistor coupled between the VDD voltage supply terminal and the VCC voltage supply terminal. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein the core protection circuit further comprises a resistor coupled between the VDD voltage supply terminal and the VCC voltage supply terminal. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the resistor has a resistance in ohms equal to 1000 to 2000 ohms times one megabit divided by a number of megabits in the array. ### Claim 9 (depends on 4) The integrated circuit of claim 4, wherein the peripheral circuit comprises row and column decoding circuitry for the array. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein the core protection circuit comprises a p-channel transistor having a source coupled to the VDD voltage supply terminal, a gate coupled to the VSS voltage supply terminal, and a drain coupled to the VCC voltage supply terminal in the core circuit. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the switch further comprises a resistor coupled between the VDD voltage supply terminal and the VCC voltage supply terminal in the core circuit. ### Claim 12 (depends on 1) The integrated circuit of claim 1, wherein the core protection circuit comprises: a p-channel transistor having a source coupled to the VDD voltage supply terminal and a drain coupled to the VCC voltage supply terminal in the core circuit; a capacitor having a first terminal coupled to the VDD voltage supply terminal and a second terminal coupled to a gate of the p-channel transistor; and a constant current source having a first terminal coupled to the gate of the p-channel transistor and a second terminal coupled to the VSS voltage supply terminal. ### Claim 13 (depends on 12) The integrated circuit of claim 12, wherein the constant current source draws a current of about 5 micro-amps. ### Claim 14 (depends on 12) The integrated circuit of claim 12, wherein the capacitor and constant current source exhibit a time constant greater than 100 nanoseconds and less than 1 milli-second. ### Claim 15 (depends on 12) The integrated circuit of claim 12, wherein the core protection circuit further comprises a resistor coupled between the VDD voltage supply terminal and the VCC voltage supply terminal in the core circuit. ### Claim 16 (depends on 1) The integrated circuit of claim 1, wherein a nominal VDD supply voltage is applied to the VDD voltage supply terminal during normal operation of the integrated circuit, and wherein the core protection circuit is further configured to disconnect the VCC voltage supply terminal from the VDD voltage supply when a voltage on the VDD voltage supply terminal exceeds a predetermined voltage greater than the nominal VDD supply voltage. ### Claim 17 (depends on 16) The integrated circuit of claim 16, wherein the predetermined voltage greater than the nominal VDD supply voltage is about 1.45 times the nominal VDD supply voltage. ### Claim 18 (depends on 16) The integrated circuit of claim 16, wherein the core protection circuit is configured to disconnect the VCC voltage supply terminal from the VDD voltage supply less than 100 pico-seconds after the voltage on the VDD voltage supply terminal exceeds the predetermined voltage. ### Claim 19 (depends on 16) The integrated circuit of claim 16, wherein the core protection circuit comprises: a first p-channel transistor having a source coupled to the VDD voltage supply terminal and a drain coupled to the VCC voltage supply terminal in the core circuit; a control circuit coupled to a gate of the first p-channel transistor. ### Claim 20 (depends on 19) The integrated circuit of claim 19, wherein the control circuit comprises: a comparator having a first input terminal coupled to receive a first voltage corresponding with a voltage on the VDD voltage supply terminal, and a second input terminal coupled to receive a second voltage corresponding with the predetermined voltage; and a second p-channel transistor having a gate coupled to an output terminal of the comparator, a source coupled to the VDD voltage supply terminal, and a drain coupled to the gate of the first p-channel transistor. ### Claim 21 (depends on 20) The integrated circuit of claim 20, further comprising an n-channel transistor having a drain coupled to the gate of the first p-channel transistor, a source coupled to the VSS voltage supply terminal, and a gate coupled to the output terminal of the comparator. ### Claim 22 (depends on 21) The integrated circuit of claim 21, wherein the n-channel transistor is smaller than the second p-channel transistor. ### Claim 23 (depends on 21) The integrated circuit of claim 21, further comprising a resistor coupled between the drain of the n-channel transistor and the gate of the first p-channel transistor. ### Claim 24 (depends on 20) The integrated circuit of claim 20, further comprising one or more diodes coupled between the VDD voltage supply terminal and the first input terminal of the comparator. ### Claim 25 (depends on 19) The integrated circuit of claim 19, further comprising a resistor coupled between the VDD voltage supply terminal and the VCC voltage supply terminal. ### Claim 26 A method of providing electrostatic discharge (ESD) protection for an integrated circuit, the method comprising: providing a VDD supply voltage to a VDD voltage supply terminal of the integrated circuit; and routing the VDD supply voltage to a VCC voltage supply terminal of a sensitive core circuit of the integrated circuit as a VCC supply voltage, such that the VCC supply voltage rises slowly with respect to a rising voltage on the VDD voltage supply terminal during power-on of the integrated circuit. ### Claim 27 (depends on 26) The method of claim 26, further comprising enabling an ESD protection circuit coupled to the VDD voltage supply terminal before the VCC supply voltage reaches a voltage that would damage the sensitive core circuit. ### Claim 28 (depends on 26) The method of claim 26, further comprising: applying a nominal VDD supply voltage to the VDD voltage supply terminal during normal operation of the integrated circuit; and disconnecting the VCC voltage supply terminal from the VDD voltage supply when a voltage on the VDD voltage supply terminal exceeds a predetermined voltage that is greater than the nominal VDD supply voltage. ### Claim 29 (depends on 28) The method of claim 28, further comprising enabling an ESD protection circuit coupled to the VDD voltage supply terminal when the voltage on the VDD voltage supply terminal exceeds the predetermined voltage.