# US 6,724,497 B1 · Image processing device which can perform a plurality of types of image processing at high speed

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- Number: US 6,724,497 B1
- Document ID: US6724497B1
- Status: Granted
- Kind: B1
- Application number: 09/484,254
- Filed: 2000-01-18
- Granted: 2004-04-20
- Earliest claimed: 1999-02-01
- Assignees: Ricoh Company, Ltd.
- Inventors: Yuji Takahashi
- Web page: https://patentgrep.com/patent/US6724497B1

## CPC

- H04N 1/40: Picture signal circuits (H04N1/387 takes precedence)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A first image processing portion, using respective synchronization signals for ‘n’ blocks of image data, performs first predetermined image processing on the image data. A second image processing portion combines the ‘n’ blocks of image data in line units, and performs second predetermined image processing on the image data using synchronization signals, the period of each of which is ‘n’ times the period of each of the respective synchronization signals. A third image processing portion again divides each line of image data into ‘n’ blocks of image data, and performs third predetermined image processing on the image data using the respective synchronization signals, the period of each of which is the original period.

## Claims

### Claim 1

An image processing device which receives image data from an image reading device which divides each line of image data into ‘n’ blocks of image data, said ‘n’ being an arbitrary number, and transfers the ‘n’ blocks of image data in synchronization with respective synchronization signals, and performs predetermined image processing on the thus-received image data, said image processing device comprising:
a first image processing portion which, using respective synchronization signals for the ‘n’ blocks of image data, performs first predetermined image processing on the image data in parallel; and
a second image processing portion which combines the ‘n’ blocks of image data in line units, and performs second predetermined image processing on the image data in parallel using synchronization signals, the period of each of which is ‘n’ times the period of each of the respective synchronization signals used by said first image processing portion.

### Claim 2 (depends on 1)

The image processing device as claimed in claim 1, further comprising:
a third image processing portion which again divides each line of image data into ‘n’ blocks of image data, and performs third predetermined image processing on the image data in parallel using respective synchronization signals, the period of each of which is the original one; and
a line-data obtaining portion which converts the ‘n’ blocks of image data output from said third image processing portion into parallel data so as to reduce the period of each of the respective synchronization signals to be 1/n times the original one, and, also, to decrease the frequency of a pixel clock, combines the ‘n’ blocks of image data in line units, and, transfers the thus-obtained image data in synchronization with a synchronization signal, the period of which is said original one, and, also, in synchronization with the pixel clock, the frequency of which is reduced.

### Claim 3

An image processing device which receives image data from an image reading device which divides each line of image data into ‘n’ blocks of image data, said ‘n’ being an arbitrary number, and transfers the ‘n’ blocks of image data in synchronization with respective synchronization signals, said image processing device comprising:
an image processing portion which performs predetermined image processing on the image data received from said image reading device, and comprises a first processing portion which, using respective synchronization signals for the ‘n’ blocks of image data, performs first predetermined image processing on the image data in parallel, and a second processing portion which combines the ‘n’ blocks of image data in line units, and performs second predetermined image processing on the thus-obtained image data in parallel using synchronization signals, the period of each of which is ‘n’ times the period of each of the respective synchronization signals used by said first image processing portion; and
an image-combination processing portion which performs processing of combining image data produced by an image producing portion and the image data output from said image processing portion.

### Claim 4 (depends on 3)

The image processing device as claimed in claim 3, wherein:
said image processing portion further comprises a third processing portion which again divides each line of image data into ‘n’ blocks of image data, and performs third predetermined image processing on the image data in parallel using respective synchronization signals, the period of each of which is the original one; and
said image-combination processing portion performs the processing of combining the image data produced by said image producing portion and the image data which is obtained as a result of the ‘n’ blocks of image data output from said third processing portion of said image processing portion being converted into a parallel data so as to reduce the period of each of the respective synchronization signals for the ‘n’ blocks of image data to be 1/n times the original one, and, also, to decreases the frequency of a pixel clock, the ‘n’ blocks of image data being combined, and, the thus-obtained image data being transferred in synchronization with a synchronization signal, the period of which is said original one, and in synchronization with the pixel clock, the frequency of which is reduced.

### Claim 5 (depends on 3)

The image processing device as claimed in claim 3, further comprising an input interface for inputting image data to said image producing portion.

### Claim 6 (depends on 3)

The image processing device as claimed in claim 3, wherein a single data bus is used for inputting the image data to said image producing portion, and, also, for outputting the image data from said image producing portion.