# US 6,724,453 B2 · Method of fabricating array substrate for use in an in-plane switching mode liquid crystal display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,453 B2 - Document ID: US6724453B2 - Status: Granted - Kind: B2 - Application number: 09/851,325 - Filed: 2001-05-09 - Published: 2001-11-29 - Granted: 2004-04-20 - Earliest claimed: 2000-05-10 - Assignees: LG.Philips LCD Co., Ltd. - Inventors: Jae-Sung Cho - Web page: https://patentgrep.com/patent/US6724453B2 ## CPC - G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]} - G02F 1/136213: {Storage capacitors associated with the pixel electrode} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A method of fabricating an array substrate (as well as an array substrate itself) for use in an IPS-LCD device prevents a short-circuit between a data line and a storage capacitor. When fabricating the array substrate for use in the IPS-LCD device, the residues of a third metallic material, which remains in step portions of the double-layered common line, cause a short-circuit between a data line and a storage capacitor. In order to prevent the short-circuit, a plurality of protrusions extending from a first layer of the double-layered common line are formed at both sides of the storage capacitor. The plural protrusions have quadrilateral-shaped holes in their central portions. By forming an etching hole at each corner of the protrusion and eliminating the residues using the etching hole, the short-circuit between the storage capacitor and the data line is obviated. Accordingly, the IPS-LCD device having a high resolution is achieved. ## Claims ### Claim 1 An array substrate for use in an IPS-LCD device, comprising: a plurality of double-layered gate lines on a substrate, wherein the double-layered gate lines are comprised of first and second layers that overlap each other; a plurality of data lines over the substrate, wherein each data line is perpendicular to each double-layered gate line, and wherein each pair of double-layered gate and data lines defines a pixel area; a double-layered common line on the substrate, wherein the double-layered common line is parallel with and spaced apart from the double-layered gate line, and wherein the double-layered common line is comprised of first and second layers that overlap each other; a plurality of protrusions extending from the first layer of the double-layered common line, wherein each protrusion has a hole in a central portion thereof; a plurality of common electrodes extending from the second layer of the double-layered common line and parallel with the data line; a common-connecting line perpendicular to and connecting the common electrodes with each other; a plurality of pixel electrodes spaced apart from and parallel with the said common electrodes, wherein each pixel electrode is located between a pair of common electrodes and corresponds to at least one common electrode; first and second pixel-connecting lines parallel with the double-layered common line and respectively connecting the pixel electrodes with each other at respective first and second ends of the pixel electrodes, wherein the second pixel-connecting line overlaps a portion of the double-layered common line to form a storage capacitor; and a switching element electrically located in one corner of the pixel area and connected with the double-layered gate and data lines, the switching element contacting the first pixel-connecting line and supplying voltage to the said pixel electrodes. ### Claim 2 (depends on 1) The array substrate according to claim 1, further comprising: a gate insulation layer covering the substrate and the double-layered gate lines and the double-layered common lines. ### Claim 3 (depends on 1) The array substrate according to claim 1, further comprising: a passivation layer formed over the swiching element and having a drain contact hole and an etching hole. ### Claim 4 (depends on 3) The array substrate according to claim 3, wherein the etching hole is formed over a portion of each protrusion. ### Claim 5 (depends on 3) The array substrate according to claim 3, wherein the switching element includes a source electrode that extends from the data line; a double-layered gate electrode that extends from the double-layered gate line; a drain electrode that contacts the first pixel-connecting line through the drain contact hole; an active layer over the double-layered gate electrode; and ohmic contact layer interposed between the active layer and the source and drain electrodes. ### Claim 6 (depends on 5) The array substrate according to claim 5, wherein the source and drain electrodes and the data lines are made of the metallic material selected from a group consisting of chromium (Cr), aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo), tantalum (Ta), tungsten (W), and antimony (Sb). ### Claim 7 (depends on 1) The array substrate according to claim 1, wherein the double-layered common line is made of the same material of the double-layered gate lines and formed in the same layer of the double-layered gate lines. ### Claim 8 (depends on 1) The array substrate according to claim 1, wherein the protrusions extended from the first layer of the double-layered common line are located on both sides of the storage capacitor. ### Claim 9 (depends on 1) The array substrate according to claim 1, wherein each protrusion has a quadrilateral shape. ### Claim 10 (depends on 1) The array substrate according to claim 1, wherein each protrusion has a quadrilateral-shaped hole in a central portion of the protrusion. ### Claim 11 (depends on 1) The array substrate according to claim 1, wherein the first layers of the double-layered gate and common lines include aluminium (Al). ### Claim 12 (depends on 1) The array substrate according to claim 1, wherein the second layers of the double-layered gate and common lines are made of Molybdenum (Mo). ### Claim 13 (depends on 1) The array substrate according to claim 1, wherein the second layers of the double-layered gate and common lines are made of Chrome (Cr). ### Claim 14 A liquid crystal display device, comprising: first and second substrates; a plurality of data lines on the first substrate; a plurality of gate lines on the first substrate perpendicular to the data lines; wherein a pixel region is defined by the intersection of one of the gate lines and one of the data lines; a common line in the pixel region parallel to the gate lines; a plurality of common electrodes in the pixel region parallel to the data lines and extending from the common line; a thin film transistor in the pixel region near the intersection of the one gate line and the one data line, the thin film transisor having a source electrode, a gate electrode and a drain electrode; a protrusion extending from the common line and having a portion located under a corner of said common electrodes; and a liquid crystal layer interposed between the first and second substrates. ### Claim 15 (depends on 14) The liquid crystal display device of claim 14, wherein at least one of said gate lines comprises a first gate line layer and a second gate line layer. ### Claim 16 (depends on 14) The liquid crystal display device of claim 14, wherein the common line comprises a first common line layer and a second common line layer. ### Claim 17 (depends on 16) The liquid crystal display device of claim 16, wherein the protrusion extends from the first common line layer. ### Claim 18 (depends on 14) The liquid crystal display device of claim 14, wherein the protrusion is a quadrilateral shape. ### Claim 19 (depends on 18) The liquid crystal display device of claim 18, wherein the protrusion is a square shape. ### Claim 20 (depends on 14) The liquid crystal display device of claim 14, wherein the protrusion includes an aperture in a central portion thereof. ### Claim 21 (depends on 14) The liquid crystal display device of claim 14, further comprising an aperture in the protrusion. ### Claim 22 (depends on 17) The liquid crystal display device of claim 17, wherein the second common line layer is on the first common line layer. ### Claim 23 (depends on 15) The liquid crystal display device of claim 15, wherein the first gate line layer comprises aluminum. ### Claim 24 (depends on 15) The liquid crystal display device of claim 15, wherein the second gate line layer comprises a metal selected from a group consisting of molybdenum (Mo), choromium (Cr) and tungsten (W). ### Claim 25 The liquid crystal display device of in the first common line layer comprises aluminum. ### Claim 26 (depends on 16) The liquid crystal display device of claim 16, wherein the second common line layer comprises a metal selected from a group consisting of molybdenum (Mo), choromium (Cr) and tungsten (W). ### Claim 27 (depends on 14) The liquid crystal display device of claim 14, further comprising an etching hole over a portion of the protrusion. ### Claim 28 (depends on 20) The liquid crystal display device of claim 20, further comprising an etching hole over the aperture.