Multiplexing digital video out on an accelerated graphics port interface

A system comprising:

• a chipset space to receive one of first and second chipsets, the first chipset supporting first and second graphics modes, the second chipset supporting second graphics mode;
• and
• an interface port coupled to one of the first and second chipsets, the interface port comprising:
• a first plurality of data and command pins corresponding to data and command signals in the first graphics mode, the first plurality of data and command pins being mapped into a second plurality of data and command pins corresponding to data and command signals in the second graphics mode, and
• a detector pin strappable to a logic level to indicate an external card is used in the first graphics mode, the detector pin being mapped into a first pin corresponding to a first signal of the second graphics mode, the first signal being ignored by the second chipset during initialization.