Display driver and display unit and electronic apparatus utilizing the same

A display drive circuit including a RAM formed of at least a plurality of memory cells provided for each pixel, each of the memory cells comprising:

• a flip-flop having first and second nodes which store logic levels complementary to each other;
• a first switching element which electrically connects a first bit line with the first node when a first word line becomes active;
• a second switching element which electrically connects a second bit line with the first node when a second word line becomes active;
• a setting circuit which sets the second node at a first logic level based on a set signal;
• and
• a circuit which outputs the logic level stored at the second node to a display read line based on a given read signal,
• the display driver comprising a set signal generation circuit which generates the set signal for each pixel, the set signal setting the second node at the first logic level for the memory cells for a pixel.

A display driver having a plurality of memory cells, each of the memory cells comprising:

• means for storing logic levels complementary to each other;
• means for electrically connecting a first bit line with a first node when a first word line becomes active;
• means for electrically connecting a second bit line with the first node when a second word line becomes active;
• means for setting a second node at a first logic level based on a set signal;
• and
• means for outputting the logic level stored at the second node to a display read line based on a given read signal,
• the display driver comprising means for generating the set signal for each pixel, the set signal setting the second node at the first logic level for the memory cells for a pixel.

The display driver as defined in

• wherein n×A (A is a natural number) pieces of the memory cells are arranged in the row direction such that
• (n×LC)×A<ΔL
• is satisfied where n represents the number of bits of gray scale data per dot;
• ΔL represents a pitch of output electrodes which output display data;
• and LC represents a pitch of the memory cells.

A method for providing a display driver with a plurality of memory cells comprising:

• storing logic levels complementary to each other;
• electrically connecting a first bit line with a first node when a first word line becomes active;
• electrically connecting a second bit line with the first node when a second word line becomes active;
• setting a second node at a first logic level based on a set signal;
• and
• outputting the logic level stored at the second node to a display read line based on a given read signal;
• and
• generating the set signal for each pixel, the set signal setting the second node at the first logic level for the memory cells for a pixel.