US 6,724,338 B1 · Method and apparatus for early comparison with a constant delay circuit

Abstract

A method and apparatus are arranged to provide an early comparison scheme for a pipelined ADC stage with a delay circuit. The pipelined ADC includes an amplifier that is biased by a precision bias circuit. The delay circuit includes inverting stages, where each inverting stage includes one or more current sources. The delay circuit is configured to provide a latch signal in response to a clocking signal for the pipelined ADC stage. The latch signal is utilized by one or more comparators for early evaluation of the output of the pipelined ADC stage. The current sources in the delay circuit may also be biased by the precision bias circuit such that variations in amplifier performance are tracked by variations in the performance of the delay circuit. Process, temperature, and power supply related variations in the timing may be minimized by the biasing arrangement of the amplifiers and the delay circuit.

Claims20

Dependent claims

An apparatus, comprising:

a precision bias circuit that is configured to provide a biasing signal;
and
a timing and control circuit that includes a first current source and a first inverter circuit, wherein the first current source is biased in response to the biasing signal, wherein the first inverter circuit is arranged to provide an output signal in response to a clock signal after a delay time, wherein the first inverter circuit is configured in cooperation with the first current source such that the delay time is associated with an operating current that is associated with the first current source, such that the sensitivity of the delay time to variations in operating conditions is reduced.

Dependencies are inferred from the claim text.

Method and apparatus for early comparison with a constant delay circuit

Life of this patent

Method and apparatus for early comparison with a constant delay circuit

Life of this patent

Abstract

Claims20