# US 6,724,329 B2 · Decision feedback equalization employing a lookup table > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,329 B2 - Document ID: US6724329B2 - Status: Granted - Kind: B2 - Application number: 10/131,444 - Filed: 2002-04-24 - Published: 2003-10-30 - Granted: 2004-04-20 - Earliest claimed: 2002-04-24 - Assignees: Intel Corporation - Inventors: Bryan K. Casper - Web page: https://patentgrep.com/patent/US6724329B2 ## CPC - H03K 5/08: by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) - H04L 25/03057: {with a recursive structure (H04L25/03031 takes precedence)} - H04L 2025/03503: {as a combination of feedback and prediction filters} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A decision feedback equalizer includes a lookup table device. The lookup table device may include a shift register and memory, or may include multiple shift registers and memories. Near-end crosstalk may be reduced using a lookup table device. Echo in a bi-directional port circuit may also be reduced using a lookup table device. ## Claims ### Claim 1 A circuit comprising: a variable offset comparator having a signal input node, a digital control input, and a digital output node; and a lookup table device coupled between the digital output node and the digital control input of the variable offset comparator. ### Claim 2 (depends on 1) The circuit of claim 1 wherein the variable offset comparator comprises: first and second differential transistor pairs; and first and second variable current generators coupled to the first and second differential transistor pairs, respectively, wherein the first and second variable current generators are coupled to be responsive to the digital control input. ### Claim 3 (depends on 1) The circuit of claim 1 wherein the variable offset comparator comprises: a voltage-to-current converter coupled between the signal input node and a current summing node; and a digital-to-analog converter having a current output, the digital-to-analog converter coupled between the digital control input and the current summing node. ### Claim 4 (depends on 1) The circuit of claim 1 wherein the lookup table device includes a shift register and a memory. ### Claim 5 (depends on 4) The circuit of claim 4 further comprising a lookup table programming control circuit to fill the memory with digital data. ### Claim 6 (depends on 1) The circuit of claim 1 wherein the lookup table device includes a finite impulse response filter including a group of taps implemented with a memory device. ### Claim 7 (depends on 6) The circuit of claim 6 wherein the finite impulse response filter further includes a plurality of groups of taps, each of the plurality of groups of taps having a shift register and a memory device. ### Claim 8 (depends on 1) The circuit of claim 1 further comprising: a driver coupled to drive an output signal on the signal input node; and an echo cancellation node coupled between the driver and the lookup table device to provide an indication of data driven by the driver to the lookup table device. ### Claim 9 (depends on 8) The circuit of claim 8 wherein the lookup table device includes: a first shift register coupled to receive data from the digital output node; a second shift register coupled to receive the indication of data driven by the driver; and a memory device coupled to receive address bits from the first and second shift registers, and coupled to provide a digital control word to the digital control input. ### Claim 10 (depends on 1) The circuit of claim 1 further comprising: a driver coupled to drive an output node other than the signal input node; and a near-end crosstalk cancellation node coupled between the driver and the lookup table device to provide an indication of data driven by the driver to the lookup table device. ### Claim 11 (depends on 10) The circuit of claim 10 wherein the lookup table device includes: a first shift register coupled to receive data from the digital output node; a second shift register coupled to receive the indication of data driven by the driver; and a memory device coupled to receive address bits from the first and second shift registers, and coupled to provide a digital control word to the digital control input. ### Claim 12 A circuit, comprising: a lookup table device including a memory device, the lookup table device to couple to a digital output node and a digital input of a variable offset comparator. ### Claim 13 (depends on 12) The circuit of claim 12 further comprising: an echo cancellation node coupled between a driver and the lookup table device to provide an indication of data driven by the driver to the lookup table device. ### Claim 14 (depends on 13) The circuit of claim 13 further comprising: a shift register coupled to receive the indication of data drive by the driver. ### Claim 15 (depends on 12) The circuit of claim 12 further comprising: a shift register coupled to receive data from the digital output node. ### Claim 16 (depends on 12) The circuit of claim 12, wherein the memory device is coupled to receive address bits from a plurality of shift registers included in the circuit, and to provide a digital control word to the digital control input. ### Claim 17 A circuit, comprising: a variable offset comparator having a digital control input and a digital output node to couple to a lookup table device. ### Claim 18 (depends on 17) The circuit of claim 17 wherein the variable offset comparator comprises: a voltage-to-current converter coupled between a signal input node and a current summing node of the variable offset comparator. ### Claim 19 (depends on 18) The circuit of claim 18 further comprising: a digital-to-analog converter to couple to the digital control input and the current summing node, and having a current output. ### Claim 20 (depends on 17) The circuit of claim 17 further comprising: a driver coupled to drive an output signal on a signal input node of the variable offset comparator; and an echo cancellation node coupled to the driver and the lookup table device to provide an indication of data driven by the driver to the lookup table device.