US 6,724,328 B1 · Byte alignment for serial data receiver

Abstract

A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Claims29

Dependent claims

A method of aligning a boundary between bytes of a deserialized serial data signal that has been input into a programmable logic device, said programmable logic device having a serial data interface with a plurality of channels, and having a programmable logic core, said method comprising:

receiving a respective serial data signal on each respective channel of said serial data interface;
for each said channel, deserializing said serial data signal, including inserting an initial candidate byte boundary between selected bits of said deserialized data signal;
transmitting said deserialized data signal with said initial candidate byte boundary from each said channel of said serial data interface to said programmable logic core;
processing said deserialized signal with said initial candidate byte boundary on each said channel in said programmable logic core to validate each said initial candidate byte boundary;
and
sending a respective byte alignment error signal from said programmable logic core to a respective channel of said serial data interface when said candidate boundary on said respective channel is determined to be invalid.

3 more elements

receiving a respective serial data signal on each respective channel of said serial data interface;
for each said channel, deserializing said serial data signal, including inserting an initial candidate byte boundary between selected bits of said deserialized data signal;
transmitting said deserialized data signal with said initial candidate byte boundary from each said channel of said serial data interface to said programmable logic core;
and
receiving a respective byte alignment error signal from said programmable logic core on a respective channel of said serial data interface when said candidate boundary is determined in said programmable logic core to be invalid.

2 more elements

Dependencies are inferred from the claim text.

Byte alignment for serial data receiver

Life of this patent

Byte alignment for serial data receiver

Life of this patent

Abstract

Claims29