# US 6,724,327 B1 · Lower latency coding/decoding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,327 B1 - Document ID: US6724327B1 - Status: Granted - Kind: B1 - Application number: 10/447,400 - Filed: 2003-05-29 - Granted: 2004-04-20 - Earliest claimed: 2003-05-29 - Assignees: Texas Instruments Incorporated - Inventors: Stephen P. Pope; John T. Coffey; Srikanth Gummadi - Web page: https://patentgrep.com/patent/US6724327B1 ## CPC - H03M 13/00: Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes (error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An electronic device may receive a packet comprising a plurality of codewords comprising pre-processing logic, a first decoder, and a second decoder. The pre-processing logic causes some of said codewords to be provided to the first decoder and other of said codewords to be provided to the second decoder. The codewords may be of different lengths and/or different code rates. Further, the first and second decoders may implement the same or different decoding technique. ## Claims ### Claim 1 An electronic device that is adapted to receive a packet comprising a plurality of codewords, comprising: pre-processing logic; a first decoder; and a second decoder; wherein said pre-processing logic causes some of said codewords to be provided to the first decoder and other of said codewords to be provided to the second decoder. ### Claim 2 (depends on 1) The electronic device of claim 1 wherein said packet includes a codeword having a different length than at least one other of said codewords. ### Claim 3 (depends on 1) The electronic device of claim 1 wherein said packet comprises a plurality of varying length codewords. ### Claim 4 (depends on 1) The electronic device of claim 1 wherein said packet comprises a plurality of progressively shorter codewords. ### Claim 5 (depends on 4) The electronic device of claim 4 wherein every other codeword in said packet is provided to the first decoder for decoding and all other codewords in said packet are provided to the second decoder for decoding in parallel. ### Claim 6 (depends on 1) The electronic device of claim 1 wherein every other codeword in said packet is provided to the first decoder for decoding and all other codewords in said packet are provided to the second decoder for decoding in parallel. ### Claim 7 (depends on 1) The electronic device of claim 1 wherein said first decoder decodes some of said codewords concurrently with the second decoder other of said codewords. ### Claim 8 (depends on 1) The electronic device of claim 1 wherein the first decoder implements a different decoding scheme than the second decoder. ### Claim 9 (depends on 1) The electronic device of claim 1 wherein the first decoder implements iterative decoding and said second decoder implements breadth-first trellis decoding. ### Claim 10 (depends on 1) The electronic device of claim 1 wherein both the first and second decoders implement iterative decoding but the second decoder implements fewer iteratives than the first decoder. ### Claim 11 (depends on 9) The electronic device of claim 9 wherein said packet comprises a plurality of varying length codewords. ### Claim 12 (depends on 1) The electronic device of claim 1 wherein the first decoder implements turbo decoding and said second decoder implements Viterbi decoding. ### Claim 13 (depends on 1) The electronic device of claim 1 wherein the first decoder implement low density parity check codes and the second decoder implements Viterbi decoding. ### Claim 14 (depends on 1) The electronic device of claim 1 wherein at least one of the codewords has a code rate that is different from a code rate in at least one other codeword. ### Claim 15 (depends on 14) The electronic device of claim 14 wherein said packet comprises a plurality of varying length codewords. ### Claim 16 Decode logic usable in a device that can receive packets comprising multiple codewords from at least one other device, comprising: pre-processing logic; a first decoder; and a second decoder; wherein said pre-processing logic causes some of said codewords to be provided to the first decoder and other of said codewords to be provided to the second decoder. ### Claim 17 (depends on 16) The decode logic of claim 16 wherein said packet includes a codeword having a different length than at least one other of said codewords. ### Claim 18 (depends on 16) The decode logic of claim 16 wherein said packet comprises a plurality of varying length codewords. ### Claim 19 (depends on 16) The decode logic of claim 16 wherein said packet comprises a plurality of progressively shorter codewords. ### Claim 20 (depends on 19) The decode logic of claim 19 wherein every other codeword in said packet is provided to the first decoder for decoding and all other codewords in said packet are provided to the second decoder for decoding in parallel. ### Claim 21 (depends on 16) The decode logic of claim 16 wherein every other codeword in said packet is provided to the first decoder for decoding and all other codewords in said packet are provided to the second decoder for decoding in parallel. ### Claim 22 (depends on 16) The decode logic of claim 16 wherein said first decoder decodes some of said codewords concurrently with the second decoder other of said codewords. ### Claim 23 (depends on 16) The decode logic of claim 16 wherein the first decoder implements a different decoding scheme than the second decoder. ### Claim 24 (depends on 16) The decode logic of claim 16 wherein the first decoder implements iterative decoding and said second decoder implements breadth-first trellis decoding. ### Claim 25 (depends on 24) The decode logic of claim 24 wherein said packet comprises a plurality of varying length codewords. ### Claim 26 (depends on 16) The decode logic of claim 16 wherein the first decoder implements turbo decoding and said second decoder implements Viterbi decoding. ### Claim 27 (depends on 16) The decode logic of claim 16 wherein at least one of the codewords has a code rate that is different from a code rate in at least one other codeword. ### Claim 28 (depends on 27) The decode logic of claim 27 wherein said packet comprises a plurality of varying length codewords. ### Claim 29 An electronic device that is adapted to receive a packet comprising a plurality of codewords, comprising: a first decoder; and a second decoder; a means for causing some of said codewords to be provided to the first decoder and other of said codewords to be provided to the second decoder. ### Claim 30 (depends on 29) The electronic device of claim 29 wherein said packet comprises a plurality of progressively shorter codewords. ### Claim 31 (depends on 29) The electronic device of claim 29 wherein said means comprises a means for providing every other codeword in said packet to the first decoder to be decoded and for providing all other codewords in said packet to the second decoder to be decoded in parallel. ### Claim 32 (depends on 29) The electronic device of claim 29 wherein the first decoder implements a different decoding scheme than the second decoder. ### Claim 33 A method, comprising: receiving a plurality of codewords forming a packet; providing at least one of said codewords to a first decoder; and providing at least one of said codewords to a second decoder; wherein the codewords include at least one codeword that has a length different from at least one other codeword. ### Claim 34 (depends on 33) The method of claim 33 wherein at least three of the codewords are of different lengths. ### Claim 35 (depends on 33) The method of claim 33 wherein all of said codewords from said packet are of different lengths. ### Claim 36 A method, comprising: receiving a plurality of codewords forming a packet; decoding at least one of said codewords by a first decoding scheme; and decoding at least one of said codewords by a second decoding scheme; wherein said first and second decoding schemes are different. ### Claim 37 (depends on 36) The method of claim 36 wherein the first decoding scheme comprises near-channel-capacity decoding and the second decoding scheme comprises a decoding scheme of lower latency than the first decoding scheme. ### Claim 38 (depends on 36) The method of claim 36 wherein the first decoding scheme comprises turbo decoding and the second decoding scheme comprises Viterbi decoding. ### Claim 39 (depends on 36) The method of claim 36 wherein at least one of the codewords has a length that differs from at least one other codeword. ### Claim 40 (depends on 36) The method of claim 36 wherein all of said codewords are of different lengths.