# US 6,724,272 B2 · Method of temperature calibrating a numerically controlled oscillator using low tolerance master crystals > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,272 B2 - Document ID: US6724272B2 - Status: Granted - Kind: B2 - Application number: 10/183,544 - Filed: 2002-06-27 - Published: 2004-01-01 - Granted: 2004-04-20 - Earliest claimed: 2002-06-27 - Assignees: Agere Systems Inc. - Inventors: Carl Stevenson - Web page: https://patentgrep.com/patent/US6724272B2 ## CPC - G01S 19/256: {relating to timing, e.g. time of week, code phase, timing offset} - H03L 1/026: {by using a memory for digitally storing correction values (H03L1/025 takes precedence)} - H03L 1/027: {by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/subtract logic circuit (H03L1/023, H03L1/026 take precedence)} - H03L 7/193: the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider - H03L 1/028: {of generators comprising piezoelectric resonators (H03L1/021, H03L1/022 take precedence; oscillation generators with a piezoelectric resonator H03B5/32)} - G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A frequency tracking circuit and method comprising a master crystal oscillator circuit is used for frequency tracking between a handset and a base station comprising a calibration subsystem for taking a temperature measurement, a reference control circuit for determining a numerical value needed to align a handset frequency with a base station frequency, an adder for adding the numerical value to a previous numerical value determined by the reference control circuit, a latch for latching the output of the adder, and a low precision master crystal oscillator for clocking the frequency of the latch. The most significant bit from the latch is input into a phase/frequency detector for forcing a voltage controlled oscillator to track a desired frequency. ## Claims ### Claim 1 A calibration subsystem for a numerically controlled oscillator comprising: a temperature sensor monitoring temperature of said numerically controlled oscillator; memory storing calibration values; and a controller controlling the transfer of said calibration values from said memory and said temperature sensor to said numerically controlled oscillator; said calibration values being adjustable to compensate for temperature variations in a particular master crystal oscillator. ### Claim 2 (depends on 1) The calibration subsystem for a numerically controlled oscillator according to claim 1, wherein: said controller transfers a digital value to said numerically controlled oscillator. ### Claim 3 The calibration subsystem for a numerically controlled oscillator comprising: a temperature sensor monitoring temperature of said numerically controlled oscillator; memory storing calibration values; and a controller controlling the transfer of said calibration values from said memory and said temperature sensor to said numerically controlled oscillator; wherein said numerically controlled oscillator comprises: a phase increment value register, an adder, and a latch. ### Claim 4 (depends on 3) The calibration subsystem for a numerically controlled oscillator according to claim 3, wherein: said latch is clocked by a low accuracy master crystal oscillator. ### Claim 5 (depends on 3) The calibration subsystem for a numerically controlled oscillator according to claim 3, wherein: said latch is 8 bits wide. ### Claim 6 (depends on 3) The calibration subsystem for a numerically controlled oscillator according to claim 3, wherein: said latch is 16 bits wide. ### Claim 7 (depends on 3) The calibration subsystem for a numerically controlled oscillator according to claim 3, wherein: accuracy of said numerically controlled oscillator is dependent on the bit width of said latch. ### Claim 8 A method of temperature calibrating a numerically controlled oscillator comprising: monitoring temperature of said numerically controlled oscillator, and producing a temperature values; storing calibration values; controlling the transfer of at least one of said calibration values and said temperature value to said numerically controlled oscillator; wherein adjustment is made during manufacture to compensate for a variation in a particular master crystal oscillator. ### Claim 9 (depends on 8) The method of temperature calibrating a numerically controlled oscillator according to claim 8, wherein: said controlling transfers a digital value to said numerically controlled oscillator. ### Claim 10 The method of temperature calibrating a numerically controlled oscillator comprising: monitoring temperature of said numerically controlled oscillator, and producing a temperature values; storing calibration values; controlling the transfer of at least one of said calibration values and said temperature value to said numerically controlled oscillator; wherein said numerically controlled oscillator latches a value added to a previous value produced by said numerically controlled oscillator. ### Claim 11 (depends on 10) The method of temperature calibrating a numerically controlled oscillator according to claim 10, wherein: said latching is clocked by a low accuracy master crystal oscillator. ### Claim 12 (depends on 10) The method of temperature calibrating a numerically controlled oscillator according to claim 10, wherein: said latching latches 8 bits. ### Claim 13 (depends on 10) The method of temperature calibrating a numerically controlled oscillator according to claim 10, wherein: said latching latches 16 bits. ### Claim 14 (depends on 10) The method of temperature calibrating a numerically controlled oscillator according to claim 10, wherein: accuracy of said numerically controlled oscillator is dependent on a bit width of said latching. ### Claim 15 A means for calibrating a numerically controlled oscillator comprising: a temperature sensor means monitoring temperature of said numerically controlled oscillator means; a memory means storing calibration values; and a controller means controlling a transfer of said calibration values from said memory means and said temperature sensor means to said numerically controlled oscillators; said calibration values being adjustable to compensate for temperature variations in a particular master crystal oscillator. ### Claim 16 (depends on 15) The means for calibrating a numerically controlled oscillator according to claim 15, wherein; said controller means transfers a digital value to said numerically controlled oscillator. ### Claim 17 The means for calibrating a numerically controlled oscillator comprising: a temperature sensor means monitoring temperature of said numerically controlled oscillator means; a memory means storing calibration values; and a controller means controlling a transfer of said calibration values from said memory means and said temperature sensor means to said numerically controlled oscillator; wherein said numerically controlled oscillator comprises: a phase increment value register, an adder, and a latch. ### Claim 18 (depends on 17) The means for calibrating a numerically controlled oscillator according to claim 17, wherein: said latch is clocked by a low accuracy master crystal oscillator. ### Claim 19 (depends on 17) The means for calibrating a numerically controlled oscillator a to claim 17, wherein: said latch is 8 bits wide. ### Claim 20 (depends on 17) The means for calibrating a numerically controlled oscillator according to claim 17, wherein: said latch is 16 bits wide. ### Claim 21 (depends on 17) The means for calibrating a numerically controlled oscillator according to claim 17, wherein: accuracy of said numerically controlled oscillator is dependent on a bit width of said latch.