Variable delay circuit, and differential voltage-controlled ring oscillator using the same, and PLL using the oscillator

A variable delay circuit for providing a delayed version of an input signal, the variable delay circuit being to be connected to an input of a load which input has a capacitance, the variable delay circuit comprising;

• an input terminal to which said input signal is applied;
• an output terminal to be connected to said input of said load;
• first and second control terminals to which first and second control signals that determine the amount of delay are applied;
• a switching circuit including:
• a first switching element comprising a p-channel MOS transistor having its drain connected to said output terminal and its source connected to a higher power supply conductor;
• and
• a second switching element comprising an n-channel MOS transistor having its drain connected to said output terminal and its source connected to a lower power supply conductor,
• an off control circuit, responsive to said input signal, for turning off one of said first and second switching elements by shorting a gate-source path of said one switching element;
• and
• a current control circuit, responsive to an off state of said second switching element, for causing said first control signal to control a first current flowing through said first switching element by providing a conductive path between said first control terminal and a gate of said first switching element, and responsive to an off state of said first switching element, for causing said second control signal to control a second current flowing through said second switching element by providing a conductive path between said second control terminal and a gate of said second switching element.