Receiver with delay insensitive to input amplitude and slew rate
AssigneeInternational Business Machines Corporation
InventorsJames David Strom, Patrick Lee Rosno
Life of this patent
Estimating the term…
Abstract
A receiver is provided with delay generally insensitive to input amplitude and slew rate. The receiver includes a first differential transistor pair having a common emitter connection. A differential input is applied to a respective base of the differential transistor pair. A pair of load transistors is connected to the respective collector of the differential transistor pair. A respective resistance is coupled to a base of the load transistors for providing a delay independent of the differential input; and a pair of bias transistors is coupled to the respective collector of the differential transistor pair for biasing the load transistors.
Claims19
A receiver having delay generally insensitive to input amplitude and slew rate comprising:
- a first differential transistor pair having a common emitter connection;
- a differential input applied to a respective base of said differential transistor pair;
- a pair of load transistors, said load transistors respectively connected to a respective collector of said differential transistor pair;
- a respective resistance coupled to a base of said load transistors for providing a delay independent of said differential input;
- and
- a pair of bias transistors coupled to said respective collector of said differential transistor pair for biasing said load transistors.
A receiver having delay generally insensitive to input amplitude and slew rate comprising:
- an input stage including a first differential transistor pair;
- a pair of load transistors, and a pair of bias transistors;
- said first differential transistor pair having a common emitter connection;
- a differential input applied to a respective base of said differential transistor pair;
- said load transistors respectively connected to a respective collector of said differential transistor pair;
- a first stage differential output provided at said respective collectors of said first differential transistor pair;
- a respective resistance coupled to a base of said load transistors for providing a delay independent of said differential input;
- said pair of bias transistors coupled to said respective collector of said differential transistor pair for biasing said load transistors;
- and
- a second stage emitter follower level shifter coupled to said input stage and receiving said differential output provided at said respective collectors of said first differential transistor pair and providing a second stage differential output.
Dependencies are inferred from the claim text.