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US 6,724,253 B2Granted
Predistortion type linearizer controlled by two control voltages
AssigneeNEC Compound Semiconductor Devices, Ltd.
InventorsGary Hau, Naotaka Iwata
Life of this patent
Estimating the term…
Abstract
In a predistortion type linearizer including a FET, an input matching circuit connected to the drain of the FET for receiving an input signal, an output matching circuit connected to the source of said the FET for outputting an output signal, and a inductor having a first terminal connected to the gate of the FET and a second terminal for receiving a first control voltage, a variable impedance circuit is connected to the second terminal of the inductor, and the impedance of the variable impedance circuit is adjusted by a second control voltage.
Claims18
A predistortion type linearizer comprising:
- a first FET having a gate, a drain and a source;
- an input matching circuit, connected to the drain of said first FET, for receiving an input signal;
- an output matching circuit, connected to the source of said first FET, for outputting an output signal;
- a first inductor having a first terminal connected to the gate of said first FET and a second terminal for receiving a first control voltage;
- and
- a variable impedance circuit, connected to the second terminal of said first inductor, an impedance of said variable impedance circuit being adjusted by a second control voltage.
3 more elements
A predistortion type linearizer comprising:
- a first FET having a gate, a drain and a source;
- an LC resonant circuit connected between the drain and source of said first FET;
- a first capacitor, connected to the drain of said first FET, for receiving an input signal;
- a grounded inductor connected to the drain of said first FET;
- a second capacitor, connected to the source of said first FET, for outputting an output signal;
- a second grounded inductor connected to the source of said first FET;
- a first inductor having a first terminal connected to the gate of said first FET and a second terminal for receiving a first control voltage;
- and
- a variable impedance circuit,
- said variable impedance circuit comprising:
- a third capacitor connected to the second terminal of said first inductor;
- a varactor diode connected between said third capacitor and ground;
- and
- a first resistor, connected to a node between said third capacitor and said varactor diode, for receiving a second control voltage.
11 more elements
A predistortion type linearizer comprising:
- a first FET having a gate, a drain and a source;
- an LC resonant circuit connected between the drain and source of said first FET;
- a first capacitor, connected to the drain of said first FET, for receiving an input signal;
- a grounded inductor connected to the drain of said first FET;
- a second capacitor, connected to the source of said first FET, for outputting an output signal;
- a second grounded inductor connected to the source of said first FET;
- a first inductor having a first terminal connected to the gate of said first FET and a second terminal for receiving a first control voltage;
- and
- a variable impedance circuit,
- said variable impedance circuit comprising:
- a third capacitor connected to the second terminal of said first inductor;
- a second FET having a gate connected to said third capacitor, a grounded drain and a grounded source;
- and
- a first resistor, connected to a node between said third capacitor and said second FET, for receiving a second control voltage.
11 more elements
A predistortion type linearizer comprising:
- a first FET having a gate, a drain and a source;
- an LC resonant circuit connected between the drain and source of said first FET;
- a first capacitor, connected to the drain of said first FET, for receiving an input signal;
- a grounded inductor connected to the drain of said first FET;
- a second capacitor, connected to the source of said first FET, for outputting an output signal;
- a second grounded inductor connected to the source of said first FET;
- a first inductor having a first terminal connected to the gate of said first FET and a second terminal for receiving a first control voltage;
- and
- a variable impedance circuit, said variable impedance circuit comprising:
- a third capacitor connected to the second terminal of said first inductor;
- a second FET having a gate, a drain connected to said third capacitor and a grounded source;
- a second inductor, connected to the drain of said second FET, for receiving a first definite voltage;
- a first resistor, connected to the drain of said second FET, for receiving a second control voltage;
- a second resistor, connected to the gate of said second FET, for receiving a second definite voltage;
- a fourth capacitor, a third FET and a fifth capacitor, connected between the gate and drain of said second FET, a gate of said third FET being connected to the drain of said second FET.
12 more elements
Dependencies are inferred from the claim text.