# US 6,724,249 B1 · Multi-level class-D amplifier by means of 3 physical levels > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,249 B1 - Document ID: US6724249B1 - Status: Granted - Kind: B1 - Application number: 10/304,784 - Filed: 2002-11-26 - Granted: 2004-04-20 - Earliest claimed: 2002-11-07 - Assignees: Dialog Semiconductor GmbH - Inventors: Johan Nilsson - Web page: https://patentgrep.com/patent/US6724249B1 ## CPC - H03F 3/2173: {of the bridge type} - H03F 2200/331: Sigma delta modulation being used in an amplifying circuit - H03F 2200/345: Pulse density modulation being used in an amplifying circuit - H03F: AMPLIFIERS ## Abstract A method to generate virtual multi-level output pulses for a Class-D Amplifier, where the time-voltage-area corresponds to a multiple of digital levels is achieved. A class-D Amplifier using PDM (Pulse Density Modulation) normally converts the input signal with a Sigma Delta Modulator into high-frequency pulses of equal width and typically drives an H-Bridge, with its 3 physical output levels. The disclosed invention however adds the methods to produce pulses with a multiple of discrete values of width and provides the method to generate a pulse length select control signal for these variable-width-pulses. Using multi-level pulse widths, in contrast to just a single pulse width, allows the reduction of the pulse-sampling rate by the same factor. Or Multi-level pulse widths allow a better quality output signal. In addition, better power efficiency is achievable. ## Claims ### Claim 1 A circuit to generate virtual multi-level output pulses for a Class-D Amplifier, where the time-voltage-area corresponds to a multiple of digital levels, comprising: means to convert the input signal into ideal PDM (Pulse Density Modulated) output pulses; means to generate a “pulse polarity” and a digital “pulse length select” signal, where said pulse length select signal represents multiple pulse-area values; means to define a set of output pulse area reference values, one for each step of said multi-level output; a length-of-pulse-integrator to determine the pulse stop time, based on the pulse start time (clock), on said digital “pulse length select” signal and based on said output pulse area reference values; a pulse generator providing the multi-level output pulses to said power driver, using said pulse start and pulse stop signals; means for a Class-D power driver to drive voltage into an output load, controlled by said power driver control pulses; and means for an output load as the amplifier output's target. ### Claim 2 (depends on 1) The circuit of claim 1 wherein said input signal is an analog signal. ### Claim 3 (depends on 1) The circuit of claim 1 wherein said input signal is a digital signal with low sampling rate and high bit resolution. ### Claim 4 (depends on 1) The circuit of claim 1 wherein said means to convert the PCM (Pulse Code Modulated) input to power driver control pulses contains a Sigma Delta Modulator. ### Claim 5 (depends on 1) The circuit of claim 1 wherein said means to generate a “pulse polarity” and a digital “pulse length select” signal is an integrated part of the Pulse Density Modulator implementation. ### Claim 6 (depends on 1) The circuit of claim 1 wherein said digital “pulse length select” signal is a multi-bit control function. ### Claim 7 (depends on 1) The circuit of claim 1 wherein said means to define the set of output pulse area references has at least 2 values. ### Claim 8 (depends on 1) The circuit of claim 1 wherein said means to define the set of output pulse area references assume a set of fixed and a priori known magnitudes. ### Claim 9 (depends on 1) The circuit of claim 1 wherein said means to define the set of output pulse area references is uses a single value, which is then further divided into said set of output pulse area references. ### Claim 10 (depends on 7) The circuit of claim 7 wherein said single value, to calculate said set of output pulse area references, receives this value as an external control definition. ### Claim 11 (depends on 1) The circuit of claim 1 wherein said means for a Class-D power driver is an H-Bridge. ### Claim 12 (depends on 1) The circuit of claim 1 wherein said means to convert the PCM (Pulse Code Modulated) input signal is implemented as an integrated digital logic function. ### Claim 13 (depends on 1) The circuit of claim 1 wherein said means to convert the PCM (Pulse Code Modulated) input signal is implemented as a calculating algorithm in a digital signal processor. ### Claim 14 (depends on 1) The circuit of claim 1 wherein said means to generate a “pulse polarity” and a digital “pulse length select” signal is implemented as an integrated digital logic function. ### Claim 15 (depends on 1) The circuit of claim 1 wherein said means to generate a “pulse polarity” and a digital “pulse length select” signal is implemented as a calculating algorithm in a digital signal processor. ### Claim 16 (depends on 1) The circuit of claim 1 wherein said length-of-pulse-integrator to determine the pulse stop time, based on said pulse start time, said digital “pulse length select” signal and said output pulse area reference values, is implemented as an analog integrated function. ### Claim 17 (depends on 1) The circuit of claim 1 wherein said length-of-pulse-integrator to determine the pulse stop time, based on said pulse start time, said digital “pulse length select” signal and said output pulse area reference values, is implemented as an integrated digital logic function. ### Claim 18 (depends on 1) The circuit of claim 1 wherein said length-of-pulse-integrator to determine said pulse stop time, based on said pulse start time, said digital “pulse length select” signal and said output pulse area reference values, is implemented as a calculating algorithm in a digital signal processor. ### Claim 19 (depends on 1) The circuit of claim 1 wherein said pulse generator providing said multi-level output pulses for said power driver is implemented as an integrated digital logic function. ### Claim 20 (depends on 1) The circuit of claim 1 wherein said pulse generator providing said multi-level output pulses for said power driver is implemented as a calculating algorithm in a digital signal processor. ### Claim 21 A method to generate virtual multi-level output pulses for a Class-D Amplifier, where the time-voltage-area corresponds to a multiple of digital levels, comprising: providing means to convert the input signal into ideal PDM (Pulse Density Modulated) power driver control pulses, means to generate a “pulse polarity” and a digital “pulse length select” signal, means to define a set of output pulse area reference values, a length-of-pulse-integrator to determine the pulse stop time, a pulse generator providing the power driver control pulses using, means for a Class-D power driver to drive voltage into an output load and means for an output load; converting said input signal into ideal PDM control pulses; generating said “pulse polarity” and said digital “pulse length select” signal, where said pulse length select signal represents multiple pulse-area values; defining said set of output pulse area reference values, one for each step of said multi-level output; determining said pulse stop time, based on said pulse start time (clock), on said digital “pulse length select” signal and based on said output pulse area reference values; generating said multi-level output pulses using said pulse start and pulse stop signals; applying said power driver control pulses to said Class-D power driver; and driving said power driver's output voltage to the output load (typically a loudspeaker). ### Claim 22 (depends on 18) The method of claim 18 wherein converting said input signal into ideal PDM control pulses is done by a processing unit containing a Sigma Delta Modulator. ### Claim 23 (depends on 21) The method of claim 21 wherein generating said “pulse polarity” and a digital “pulse length select” signal is an integrated with the method to convert said Pulse Density Modulator signal as a combined function. ### Claim 24 (depends on 21) The method of claim 21 wherein defining the set of output pulse area references uses at least 2 values. ### Claim 25 (depends on 21) The method of claim 21 wherein defining the set of output pulse area references assume a set of fixed and a priori known magnitudes. ### Claim 26 (depends on 21) The method of claim 21 wherein defining the set of output pulse area references takes a single fixed value and then further divides it into said set of output pulse area references. ### Claim 27 (depends on 21) The method of claim 21 wherein an H-Bridge is used for driving voltage to said output load. ### Claim 28 (depends on 21) The method of claim 21 wherein converting said input signal into ideal PDM power driver control pulses is implemented by an integrated digital logic function. ### Claim 29 (depends on 21) The method of claim 21 wherein converting said input signal into ideal PDM power driver control pulses is implemented by a calculating algorithm in a digital signal processor. ### Claim 30 (depends on 21) The method of claim 21 wherein generating said “pulse polarity” and said digital “pulse length select” signal is implemented by an integrated digital logic function. ### Claim 31 (depends on 21) The method of claim 21 wherein generating said “pulse polarity” and said digital “pulse length select” signal is implemented by a calculating algorithm in a digital signal processor. ### Claim 32 (depends on 21) The method of claim 21 wherein determining said pulse stop time, based on said pulse start time (clock), on said digital “pulse length select” signal and based on said output pulse area reference values is implemented by an integrated analog function. ### Claim 33 (depends on 21) The method of claim 21 wherein determining said pulse stop time, based on said pulse start time (clock), on said digital “pulse length select” signal and based on said output pulse area reference values is implemented by an integrated digital logic function. ### Claim 34 (depends on 21) The method of claim 21 wherein determining said pulse stop time, based on said pulse start time (clock), on said digital “pulse length select” signal and based on said output pulse area reference values is implemented by a calculating algorithm in a digital signal processor. ### Claim 35 (depends on 21) The method of claim 21 wherein generating said multi-level power driver control pulses is performed in an integrated digital logic function. ### Claim 36 (depends on 21) The method of claim 21 wherein generating said multi-level power driver control pulses is performed in a calculating algorithm in a digital signal processor.