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US 6,724,243 B2Granted
Bias circuit with voltage and temperature stable operating point
AssigneeSTMicroelectronics S.r.l.
InventorFrancesco La Rosa
Life of this patent
Estimating the term…
Abstract
A bias circuit integrated on a silicon wafer includes first, second and third branches. The first branch includes a first PMOS transistor in series with a first NMOS transistor. The second branch includes a second PMOS transistor, a second NMOS transistor and an electric resistor in series. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The first branch and the second branch are arranged as a current mirror. The third branch includes a third PMOS transistor in series with a third NMOS transistor. The third PMOS and NMOS transistors are arranged to maintain a drain voltage of the first PMOS transistor that is substantially identical to a drain voltage of the second PMOS transistor.
Claims29
A bias circuit comprising:
- a semiconductor substrate;
- a first branch on said semiconductor substrate and comprising a first PMOS transistor and a first NMOS transistor connected in series therewith, said first PMOS transistor comprising a gate and a drain, and said first NMOS transistor comprising a gate;
- a second branch on said semiconductor substrate and connected to said first branch for forming a current mirror, said second branch comprising a second PMOS transistor, at least one second NMOS transistor connected in series therewith, and a resistive element connected in series with said at least one second NMOS transistor, said second PMOS transistor comprising a gate and a drain, and said at least one second NMOS transistor comprising a gate connected to the gate of said first NMOS transistor, said resistive element having a temperature coefficient so that a resistive value thereof remains stable during temperature variations so that a current passing through said second branch is relatively stable;
- and
- a third branch on said semiconductor substrate and comprising a third PMOS transistor and a third NMOS transistor connected thereto, said third branch being connected to said first and second branches for maintaining a voltage on the drain of said first PMOS transistor that is substantially equal to a voltage on the drain of said second PMOS transistor.
2 more elements
A bias circuit comprising:
- a semiconductor substrate;
- a first branch on said semiconductor substrate and comprising a first transistor of a first conductivity type and a first transistor of a second conductivity type connected in series therewith, said first transistor of the first conductivity type comprising a control terminal and a conducting terminal, and said first transistor of the second conductivity type comprising a control terminal;
- a second branch on said semiconductor substrate and connected to said first branch for forming a current mirror, said second branch comprising a second transistor of the first conductivity type, at least one second transistor of the second conductivity type connected in series therewith, and a resistive element connected in series with said at least one second transistor of the second conductivity type, said second transistor of the first conductivity type comprising a control terminal and a conducting terminal, and said at least one second transistor of the second conductivity type comprising a control terminal connected to the control terminal of said first transistor of the second conductivity type, said resistive element having a temperature coefficient so that a resistive value thereof remains stable during temperature variations so that a current passing through said second branch is relatively stable;
- and
- a third branch on said semiconductor substrate and comprising a third transistor of the first conductivity type and a third transistor of the second conductivity type connected thereto, said third branch being connected to said first and second branches for maintaining a voltage on the conducting terminal of said first transistor of the first conductivity type that is substantially equal to a voltage on the conducting terminal of said second transistor of the first conductivity type.
2 more elements
A method for making a bias circuit comprising:
- forming a first branch on a semiconductor substrate comprising a first transistor of a first conductivity type and a first transistor of a second conductivity type connected in series therewith, the first transistor of the first conductivity type comprising a control terminal and a conducting terminal, and the first transistor of the second conductivity type comprising a control terminal;
- forming a second branch on the semiconductor substrate connected to the first branch for forming a current mirror, the second branch comprising a second transistor of the first conductivity type, at least one second transistor of the second conductivity type connected in series therewith, and a resistive element connected in series with the at least one second transistor of the second conductivity type, the second transistor of the first conductivity type comprising a control terminal and a conducting terminal, and the at least one second transistor of the second conductivity type comprising a control terminal connected to the control terminal of the first transistor of the second conductivity type, the resistive element having a temperature coefficient so that a resistive value thereof remains stable during temperature variations so that a current passing through the second branch is relatively stable;
- and
- forming a third branch on the semiconductor substrate and comprising a third transistor of the first conductivity type and a third transistor of the second conductivity type connected thereto, the third branch being connected to the first and second branches for maintaining a voltage on the conducting terminal of the first transistor of the first conductivity type that is substantially equal to a voltage on the conducting terminal of the second transistor of the first conductivity type.
1 more element
Dependencies are inferred from the claim text.