# US 6,724,239 B2 · Voltage boost circuit and low supply voltage sampling switch circuit using same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,239 B2 - Document ID: US6724239B2 - Status: Granted - Kind: B2 - Application number: 10/156,613 - Filed: 2002-05-28 - Published: 2003-01-30 - Granted: 2004-04-20 - Earliest claimed: 2001-07-24 - Assignees: Analog Devices, Inc. - Inventors: Colin Price; Mark Stephen Power - Web page: https://patentgrep.com/patent/US6724239B2 ## CPC - H03K 17/063: {in field-effect transistor switches} - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A voltage boost circuit includes a boost capacitor; a charge circuit for charging in the charging mode the boost capacitor to a supply voltage, the charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of the boost capacitor and a back gate isolation circuit connected to the back gate of the charging MOS switch and including a first switch for connecting the back gate to the supply voltage for reverse biasing the back gate in the charging mode and the second switch for connecting the back gate to the one terminal of the boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; and a boost bias voltage and a boost switch for connecting the second terminal of the boost capacitor to the boost bias voltage in the boost mode. ## Claims ### Claim 1 A voltage boost circuit comprising: a boost capacitor; a charging circuit for charging in the charging mode said boost capacitor to a supply voltage; said charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of said boost capacitor and a back gate isolation circuit connected to the back gate of said charging MOS switch and including a first switch for connecting said back gate to said supply voltage for reverse biasing said back gate in the charging mode and a second switch for connecting said back gate to said one terminal of said boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; a boost bias voltage and a boost switch for connecting the second terminal of said boost capacitor to said boost bias voltage in the boost mode; and a driving circuit having at least one stage with its supply connected to one terminal of the boost capacitor for providing driving levels of the correct voltage to the charging MOS switch in both the charging mode and the boost mode. ### Claim 2 (depends on 1) The voltage boost circuit of claim 1 in which said supply voltage is positive and said charging MOS switch includes a PMOS switch. ### Claim 3 (depends on 1) The voltage boost circuit of claim 1 in which said supply voltage is negative and said charging MOS switch includes an NMOS switch. ### Claim 4 (depends on 1) The voltage boost circuit of claim 1 in which said first and second switches each have their back gate connected to said back gate of said charging MOS switch. ### Claim 5 (depends on 1) The voltage boost circuit of claim 1 in which said boost bias voltage is an independent reference voltage. ### Claim 6 (depends on 5) The voltage boost circuit of claim 5 in which said boost bias voltage is adjustable. ### Claim 7 A low supply voltage sampling switch circuit with a voltage boost circuit comprising: a boost capacitor; a charging circuit for charging in the charging mode said boost capacitor to a supply voltage, said charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of said boost capacitor and a back gate isolation circuit connected to the back gate of said charging MOS switch and including a first switch for connecting said back gate to said supply voltage for reverse biasing said back gate in the charging mode and a second switch for connecting said back gate to said one terminal of said boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; a boost bias voltage and a boost switch for connecting the second terminal of said boost capacitor to said boost bias voltage in the boost mode; an MOS sampling switch; a boost switch for interconnecting in said boost mode said one terminal of said boost capacitor with the gate of said sampling switch for maintaining said sampling switch in the conducting state; and a driving circuit having at least one stage with its supply connected to one terminal of the boost capacitor for providing driving levels of the correct voltage to the charging MOS switch in both the charging mode and the boost mode. ### Claim 8 (depends on 7) The low supply voltage sampling switch circuit of claim 7 in which said supply voltage is positive, said charging MOS switch includes a PMOS switch and said charging MOS sampling switch includes an NMOS switch and said sampling switch conducts even at higher input voltages. ### Claim 9 (depends on 7) The low supply voltage sampling switch circuit of claim 7 in which said supply voltage is negative, said charging MOS switch is an NMOS switch and said charging MOS sampling switch is a PMOS switch and said sampling switch conducts even at lower input voltages. ### Claim 10 (depends on 7) The low supply voltage sampling switch circuit of claim 7 in which said first and second switches each have their back gates connected to said back gate of said charging MOS switch. ### Claim 11 (depends on 7) The low supply voltage sampling switch circuit of claim 7 in which said boost bias voltage is an independent reference voltage. ### Claim 12 (depends on 7) The low supply voltage sampling switch circuit of claim 7 in which boost bias voltage is adjustable. ### Claim 13 A voltage boost circuit comprising: a boost capacitor; a charging circuit for charging in the charging mode said boost capacitor to a supply voltage; said charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of said boost capacitor and a back gate isolation circuit connected to the back gate of said charging MOS switch and including a first switch for connecting said back gate to said supply voltage for reverse biasing said back gate in the charging mode and a second switch for connecting said back gate to said one terminal of said boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; and a boost bias voltage and a boost switch for connecting the second terminal of said boost capacitor to said boost bias voltage in the boost mode, wherein said boost bias voltage is an independent reference voltage. ### Claim 14 (depends on 13) The voltage boost circuit of claim 13 in which said boost bias voltage is adjustable. ### Claim 15 A low supply voltage sampling switch circuit with a voltage boost circuit comprising: a boost capacitor; a charging circuit for charging in the charging mode said boost capacitor to a supply voltage, said charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of said boost capacitor and a back gate isolation circuit connected to the back gate of said charging MOS switch and including a first switch for connecting said back gate to said supply voltage for reverse biasing said back gate in the charging mode and a second switch for connecting said back gate to said one terminal of said boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; a boost bias voltage and a boost switch for connecting the second terminal of said boost capacitor to said boost bias voltage in the boost mode, wherein said boost bias voltage is an independent reference voltage; an MOS sampling switch; and a boost switch for interconnecting in said boost mode said one terminal of said boost capacitor with the gate of said sampling switch for maintaining said sampling switch in the conducting state. ### Claim 16 (depends on 15) The low supply voltage sampling switch circuit of claim 15 in which said boost bias voltage is adjustable. ### Claim 17 (depends on 1) The voltage boost circuit of claim 1 in which said boost bias voltage is adjustable. ### Claim 18 (depends on 7) The low supply voltage sampling switch circuit of claim 7 in which said boost bias voltage is adjustable.