Dual tristate path output buffer control
AssigneeCypress Semiconductor Corporation
InventorJonathan F. Churchill
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.
Claims22
An apparatus comprising:
- a first circuit configured to generate two or more first control signals in response to (i) a clock signal and (ii) one or more second control signals;
- and
- a second circuit (i) coupled to said first circuit via one or more path circuits and (ii) configured to present an output signal in response to said two or more first control signals, wherein all of said two or more first control signals have a preferred edge skew.
An apparatus for controlling buffer circuits comprising:
- means for generating two or more first control signals in response to (i) a clock signal and (ii) one or more second control signals;
- and
- means for generating an output signal in response to said one two or more first control signals, wherein all of said two or more first control signals have a preferred edge skew.
A method for controlling buffer circuits comprising the steps of:
- (A) generating two or more first control signals in response to (i) a clock signal and (ii) one or more second control signals;
- and
- (B) generating an output signal in response to said two or more first control signals, wherein all of said two or more first control signals have a preferred edge skew.
Dependencies are inferred from the claim text.