Clock signal propagation gate and semiconductor integrated circuit including same

A semiconductor integrated circuit comprising:

• a clock signal interconnect line for propagating a rising edge of a clock signal;
• a buffer on said clock signal interconnect line;
• at least one clock signal propagation gate on said clock signal interconnect line, said at least one clock signal propagation gate including
• (a) an inverter including
• a first MOS transistor of a first conductivity type having a drain, a gate receiving the clock signal, and a source connected to a first potential point, and
• a second MOS transistor of a second conductivity type having a source connected to a second potential point, a drain connected to said drain of said first MOS transistor, and a gate connected to said gate of said first MOS transistor, and
• (b) a logic gate including
• a third MOS transistor of said second conductivity type having a gate connected directly to said drain of said first MOS transistor and to said drain of said second MOS transistor, a source connected to said second potential point, and a drain, said third MOS transistor having a current-driving capability greater than that of said first MOS transistor,
• a fourth MOS transistor of said first conductivity type having a gate, a drain connected to said drain of said third MOS transistor, and a source,
• a fifth MOS transistor of said first conductivity type having a drain connected to said source of said fourth MOS transistor, a source connected to said first potential point, and a gate, and
• a sixth MOS transistor of said second conductivity type having a drain connected to said drain of said third MOS transistor to serve as an output of said logic gate, a source connected to said second potential point, and a gate,
• said gate of one of said fourth and fifth MOS transistors being connected to said gate of said third MOS transistor, said gate of the other of said fourth and fifth MOS transistors being connected to said gate of said sixth MOS transistor,
• wherein a transition of said clock signal from a first potential at said first potential point to a second potential at said second potential point propagates to said output of said logic gate when a logic corresponding to said second potential point is applied to said gate of the other of said fourth and fifth MOS transistors and to said gate of said sixth MOS transistor, and
• wherein said at least one clock signal propagation gate propagates said clock signal when said first conductivity type is an n type, said second conductivity type is a p type, and a logic “high” is applied to the gates of said fourth and fifth MOS transistors;
• and
• a sequential circuit at an end point of said clock signal interconnect line, said sequential circuit being operated on said rising edge of said clock signal propagating through said clock signal interconnect line.

A semiconductor integrated circuit comprising:

• a clock signal interconnect line for propagating a falling edge of a clock signal;
• a buffer on said clock signal interconnect line;
• at least one clock signal propagation gate on said clock signal interconnect line, said at least one clock signal propagation gate including
• (a) an inverter including
• a first MOS transistor of a first conductivity type having a drain, a gate receiving the clock signal, and a source connected to a first potential point, and
• a second MOS transistor of a second conductivity type having a source connected to a second potential point, a drain connected to said drain of said first MOS transistor, and a gate connected to said gate of said first MOS transistor, and
• (b) a logic gate including
• a third MOS transistor of said second conductivity type having a gate connected directly to said drain of said first MOS transistor and to said drain of said second MOS transistor, a source connected to said second potential point, and a drain, said third MOS transistor having a current-driving capability greater than that of said first MOS transistor,
• a fourth MOS transistor of said first conductivity type having a gate, a drain connected to said drain of said third MOS transistor, and a source,
• a fifth MOS transistor of said first conductivity type having a drain connected to said source of said fourth MOS transistor, a source connected to said first potential point, and a gate, and
• a sixth MOS transistor of said second conductivity type having a drain connected to said drain of said third MOS transistor to serve as an output of said logic gate, a source connected to said second potential point, and a gate,
• said gate of one of said fourth and fifth MOS transistors being connected to said gate of said third MOS transistor, said gate of the other of said fourth and fifth MOS transistors being connected to said gate of said sixth MOS transistor,
• wherein a transition of said clock signal from a first potential at said first potential point to a second potential at said second potential point propagates to said output of said logic gate when a logic corresponding to said second potential point is applied to said gate of the other of said fourth and fifth MOS transistors and to said gate of said sixth MOS transistor, and
• wherein said at least one clock signal propagation gate propagates said clock signal when said first conductivity type is a p type, said second conductivity type is an n type, and a logic “low ” is applied to the gates of said fourth and fifth MOS transistors;
• and
• a sequential circuit at an end point of said clock signal:interconnect line, said sequential circuit being operated on said falling edge of said clock signal propagating through said clock signal interconnect line.