US 6,724,228 B2Granted

Clock generating circuit capable of generating internal clock accurately synchronized with external clock

AssigneeRenesas Technology Corp.

InventorYasuhiro Kashiwazaki

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Abstract

A phase difference between a feedback clock signal corresponding to an internal clock signal generated via a variable delay line and a buffered clock signal corresponding to an external clock signal is detected by a phase detector, and a result of detection is transferred via a shifting circuit. When a down signal from the shifting circuit is activated by a delay control circuit, the down instruction signal is forcibly maintained to be active for a predetermined clock cycle period. When the down instruction signal becomes inactive from the active state, a count control circuit sets a count unit of the counting circuit to the minimum value. The delay amount of the variable delay line is set according to an output count bit of the counting circuit. Therefore, it is possible to reduce the number of clock cycles required until an internal clock signal is synchronized in phase with the external clock signal.

Claims17

Dependent claims

Clock generation circuitry comprising:

an internal clock producing circuit for producing an internal clock signal in accordance with an external clock signal;
a phase difference detecting circuit for detecting a phase difference between said internal clock signal and said external clock signal;
a phase relation adjusting circuit according to an output signal of said phase difference detection circuit, for continuously maintaining a predetermine state for a predetermined number of clock cycle(s) when a phase relation between said internal clock signal and said external clock signal becomes said predetermined state, and releasing a maintained, predetermined state upon reaching to said predetermined number of clock cycle(s);
a phase adjusting circuit for adjusting a phase of said internal clock signal in accordance with an output signal of said phase relation adjusting circuit;
and
a delay control circuit for setting a phase adjustment unit of said phase adjusting circuit to a first delay amount until said predetermined state by said phase relation adjusting circuit is released and for setting the phase adjustment unit of said phase adjusting circuit to a second delay amount smaller than said first delay amount in response to release of said predetermined state.

3 more elements

Clock generation circuitry comprising:

an internal clock producing circuit for generating an internal clock signal in accordance with an external clock signal;
a phase difference detecting circuit for detecting a phase difference between said internal clock signal and said external clock signal;
a phase adjusting circuit for adjusting a phase difference between said internal clock signal and said external clock signal in accordance with an output signal of said phase difference detecting circuit;
and
a delay control circuit for adjusting a phase adjustment unit of said phase adjusting circuit in accordance with the output-signal of said phase difference detecting circuit, said delay control circuit increasing said phase adjustment unit from a first value to a second value for a predetermined cycle period in response to a predetermined state indication of the output signal of said phase difference detecting circuit, and setting said phase adjustment unit to a minimum value smaller than said first value in subsequent cycles.

2 more elements

Clock generation circuitry comprising:

an internal clock producing circuit for generating an internal clock signal in accordance with an external clock signal;
a phase difference detecting circuit for detecting a phase difference between said internal clock signal and said external clock signal;
a phase adjusting circuit for adjusting a phase difference between said internal clock signal and said external clock signal in accordance with an output signal of said phase difference detecting circuit;
and
a delay control circuit for adjusting a phase adjustment unit of said phase adjusting circuit in accordance with an output signal of said phase difference detecting circuit, said delay control circuit initializing said phase adjustment unit to a first value greater than a minimum value, and setting said phase adjustment unit to said minimum value in response to release of a predetermined state indication of the output signal of said phase difference detecting circuit.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/359,679Filed 7 Feb 2003
Priority: JP 2002-20541115 Jul 2002
Published: US 2004/0008064 A115 Jan 2004
Granted: 20 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03L 7/0805
Details of the phase-locked loop: the loop being adapted to provide an additional control signal for use outside the loop
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
H03K 5/131
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: digitally controlled
H03K 5/133
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: using a chain of active delay…