US 6,724,223 B2Granted

Semiconductor device used in two systems having different power supply voltages

AssigneeRenesas Technology Corp.

InventorsTetsuichiro Ichiguchi, Tsutomu Nagasawa, Tadaaki Yamauchi, Zengcheng Tian, Makoto Suwa, Junko Matsumoto, Takeo Okamoto, Hideki Yonetani

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Abstract

A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.

Claims16

Dependent claims

A semiconductor device having a first mode in which said semiconductor device is driven by a first power supply voltage and receives a first signal having an amplitude voltage lower than said first power supply voltage, and a second mode in which said semiconductor device is driven by a second power supply voltage lower than said first power supply voltage and receives a second signal having a second amplitude voltage lower than said second power supply voltage, said semiconductor device comprising:

a first logic circuit activated in said first mode to be driven by a first internal power supply voltage equal in level to said second power supply voltage, detecting whether said first signal is higher in level than a first threshold voltage, and outputting a signal of level according to a detection result;
a second logic circuit activated in said second mode to be driven by a second internal power supply voltage lower than said first internal power supply voltage, detecting whether said second signal is higher in level than a second threshold voltage, and outputting a signal of level according to a detection result;
and
an internal circuit performing a predetermined operation in response to output signals of said first and second logic circuits.

1 more element

A semiconductor device having a first mode in which said semiconductor device receives a first output power supply voltage, and a second mode in which said semiconductor device receives a second output power supply voltage lower than said first output power supply voltage, said semiconductor device comprising:

an internal circuit performing a predetermined operation;
and
an output circuit driven by said first and second output power supply voltages, and outputting a signal generated in said internal circuit to an outside of said semiconductor device, wherein
said output circuit includes:
a first P-type transistor having a first electrode receiving said first and second output power supply voltages, and a second electrode connected to an output node;
a voltage supply circuit outputting a ground voltage in said first mode, and outputting a predetermined negative voltage in said second mode;
and
a switching element having one electrode connected to a gate electrode of said first P-type transistor and the other electrode receiving an output voltage of said voltage supply circuit, and become conductive or nonconductive according to the signal generated in said internal circuit.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/287,643Filed 5 Nov 2002
Priority: JP 2002-14331717 May 2002
Published: US 2003/0213972 A120 Nov 2003
Granted: 20 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 7/225
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock input buffers
G11C 5/14
Details of stores covered by group G11C11/00: power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or…
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 11/4074
For memory cells of the field-effect type: power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage…