# US 6,724,222 B2 · Programmable logic with lower internal voltage circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,222 B2 - Document ID: US6724222B2 - Status: Granted - Kind: B2 - Application number: 10/366,814 - Filed: 2003-02-13 - Published: 2003-06-26 - Granted: 2004-04-20 - Earliest claimed: 1996-05-28 - Assignees: Altera Corporation - Inventors: Rakesh H. Patel; John E. Turner; John D. Lam; Wilson Wong - Web page: https://patentgrep.com/patent/US6724222B2 ## CPC - H03K 19/018585: {programmable} - H03K 19/0027: {in field effect transistor circuits} - H03K 19/00315: {in field-effect transistor circuits} - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A technique and circuitry interfaces a programmable logic integrated circuit compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, an on-chip voltage less than the external supply level of the programmable logic integrated circuit is provided to a core portion of a programmable logic integrated circuit by way of a conversion transistor. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. Externally, the programmable logic integrated circuit will interface with an external supply voltage level. The input and output signals to and from the programmable logic integrated circuit will be compatible with the external supply level. ## Claims ### Claim 1 A programmable logic integrated circuit comprising: a logic array block, programmably configurable to perform logical functions; an output driver circuit coupled to a first voltage supply; and a voltage down converter circuit, coupled to a second voltage supply to generate a third voltage supply having a voltage level below the second voltage supply, wherein the logic array block is coupled to the third voltage supply and the voltage down converter comprise: a conversion transistor coupled between the second voltage supply and to third voltage supply; and an amplifier circuit coupled to receive to third voltage supply and feed back a control signal to the conversion transistor. ### Claim 2 (depends on 1) The programmable logic integrated circuit of claim 1 wherein the conversion transistor is formed by a plurality of transistors coupled in parallel. ### Claim 3 (depends on 1) The programmable logic integrated circuit of claim 1 further comprising: a level shifter circuit coupled to the first voltage supply, wherein a logical output signal from the logic array block is programmably coupled using a programmable interconnect line to the level shifter circuit to be output using the output driver. ### Claim 4 (depends on 1) The programmable logic integrated circuit of claim 1 wherein the amplifier circuit comprises a PMOS transistor and an NMOS transistor coupled in series between the second voltage supply and a ground potential. ### Claim 5 (depends on 1) The programmable logic integrated circuit of claim 1 wherein a level of the first voltage supply is at or about a level of the second voltage supply. ### Claim 6 (depends on 1) The programmable logic integrated circuit of claim 1 wherein a first ground voltage supply is coupled to the output driver and a second ground voltage supply is coupled to the logic array block. ### Claim 7 (depends on 6) The programmable logic integrated circuit of claim 6 further comprising: a first transistor coupled between the second voltage supply and a first node, wherein a gate electrode of the first transistor is coupled to the second voltage supply; and a second transistor coupled between the first node and a gate electrode of the conversion transistor, wherein a gate electrode of the second transistor is coupled to the first node. ### Claim 8 (depends on 7) The programmable logic integrated circuit of claim 7 wherein to first and second transistors have a thicker oxide than transistors used in the logic array block. ### Claim 9 (depends on 1) The programmable logic integrated circuit of claim 1 wherein the conversion transistor has a thicker oxide than transistors used in the logic array block. ### Claim 10 (depends on 1) The programmable logic integrated circuit of claim 1 wherein input to the logic array block is compatible with a voltage range including a level of the third voltage supply and output from the output driver is compatible with a voltage range including a level of the first voltage supply. ### Claim 11 (depends on 1) The programmable logic integrated circuit of claim 1 wherein the logic array block is in a core position of the integrated circuit and the conversion transistor is between an edge of the integrated circuit and the core position. ### Claim 12 (depends on 11) The programmable logic integrated circuit of claim 11 wherein the conversion transistor is between at least two edges of the integrated circuit and the core portion. ### Claim 13 (depends on 11) The programmable logic integrated circuit of claim 11 wherein the conversion transistor is between at least three edges of the integrated circuit and the core position. ### Claim 14 (depends on 11) The programmable logic integrated circuit of claim 11 wherein the conversion transistor surrounds the core position of the integrated circuit. ### Claim 15 (depends on 11) The programmable logic integrated circuit of claim 11 wherein the conversion transistor is between at least two different edges of the integrated circuit and the core portion. ### Claim 16 (depends on 11) The programmable logic integrated circuit of claim 11 wherein to conversion transistor is between at least three different edges of the integrated circuit and the core portion. ### Claim 17 (depends on 11) The programmable logic integrated circuit of claim 11 wherein the conversion transistor is between at least four different edges of the integrated circuit and the core portion. ### Claim 18 (depends on 1) The programmable logic integrated circuit in claim 1 wherein the first voltage supply is coupled to the second voltage supply. ### Claim 19 (depends on 1) The programmable logic integrated circuit of claim 1 wherein the output circuit comprises a first transistor comprising a body connection and the integrated circuit further comprises: a second transistor coupled between the first voltage supply and the body connection, wherein a gate electrode of the second transistor is coupled to a first node, and the first node is coupled to a pin of the integrated circuit. ### Claim 20 (depends on 19) The programmable logic integrated circuit of claim 19 wherein between the pin and the first node is a resistance element. ### Claim 21 (depends on 19) The programmable logic integrated circuit of claim 19 further comprising: a third transistor coupled between the first node and the body connection, wherein a gate electrode of the third transistor is coupled to the first voltage supply. ### Claim 22 (depends on 19) The programmable logic integrated circuit of claim 19 further comprising: a third transistor coupled between the first voltage supply and the body connection, wherein a gate electrode of the third transistor is coupled to the body connection. ### Claim 23 (depends on 19) The programmable logic integrated circuit of claim 19 further comprising: a third transistor coupled between the first node and to body connection, wherein a gate electrode of the third transistor is coupled to the body connection.