Method and apparatus for reduced pin count package connection verification
AssigneeInternational Business Machines Corporation
InventorsMichael L. Combs, Donald L. Wheater
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Abstract
A method and apparatus for testing the chip-to-package connectivity of a common I/O of a semiconductor chip is disclosed which uses reduced pin count testing methods. The method includes driving a test signal transition onto a control pad of a semiconductor chip with a weak driver and comparing the transition rise time with a threshold value. For an I/O with a faulty chip-to-package connection, the rise time is much faster than for an I/O with a completed chip-to-package connection. Additional impedances may also be added to the tester fixturing to increase the sensitivity of the test equipment to the capacitance of the I/O connections.
Claims20
A method of reduced pin count testing a chip-to-package connectivity of a semiconductor device, the method comprising:
- providing an I/O driver and an I/O receiver on the semiconductor device, wherein a common I/O of the semiconductor device is electrically coupled to the driver and to the receiver, and wherein the common I/O is electrically interposed between the driver and the receiver;
- launching a transition signal from the driver;
- observing a response of the transition signal at a point within the semiconductor device;
- and
- determining whether a chip-to-package connection associated with the common I/O is faulty from the response of the transition signal.
An apparatus configured to launch a test signal to a common I/O of a semiconductor device from an I/O driver on the semiconductor device which is associated with the common I/O using reduced pin count testing, the apparatus comprising:
- a test fixture configured to couple to the common I/O of the semiconductor device;
- an I/O receiver on the semiconductor device, wherein the common I/O is electrically coupled to the driver and to the receiver, and wherein the common I/O is electrically interposed between the driver and the receiver;
- a weak driver impedance coupled between the driver and the test fixture;
- wherein the apparatus is configured to launch the test signal through the weak driver impedance and the common I/O to the test fixture and evaluate a characteristic of a response to the test signal to determine whether a chip-to-package connection associated with the common I/O is faulty.
Dependencies are inferred from the claim text.