Method for testing signal paths between an integrated circuit wafer and a wafer tester

A method for measuring resistance of signal paths within an interconnect structure for interconnecting ports of an integrated circuit (IC) tester with at least three first test points arranged on an IC wafer to be tested, the method comprising the steps of:

• providing a reference wafer having thereon at least three second test points in an arrangement substantially similar to an arrangement of said at least three first test points on said IC wafer, and having a conductor interconnecting said at least three second test points;
• employing said interconnect structure to interconnect each of said at least three second test points to a separate one of said ports;
• and
• transmitting test signals between at least three unique pairs of said at least three ports.

A method for testing signal paths within a interconnect structure for interconnecting ports of an integrated interconnect (IC) tester with first test points arranged on an IC wafer to be tested, the method comprising the steps of:

• providing a reference wafer having thereon a plurality of second test points in an arrangement substantially similar to an arrangement of said first test points on said IC wafer, having a reference point, and having a conductor interconnecting said second test points with said reference point;
• employing said interconnect structure to interconnect each of said second test points and said reference point with a separate one of said ports;
• and
• programming said IC tester to transmit a test signal from one of said ports interconnected to one of said second test points to another of said ports connected to said reference point via said signal paths within said interconnect structure and said conductor.

A method for testing signal paths within a interconnect structure for interconnecting ports of an integrated circuit (IC) tester with first test points arranged on an IC wafer to be tested, the method comprising the steps of:

• providing a reference wafer having thereon a plurality of second test points in an arrangement substantially similar to an arrangement of said first test points on said IC wafer, and having means for generating a test signal at said second test points;
• employing said interconnect structure to interconnect each of said second test points with a separate one of said ports;
• and
• programming said IC tester to monitor said ports to determine whether said test signal arrives at said ports.

A method for measuring resistance of signal paths within a interconnect structure for interconnecting ports of an integrated circuit (IC) tester with first test points arranged on an IC wafer to be tested, the method comprising the steps of:

• providing a reference wafer having thereon a plurality of second test points in an arrangement substantially similar to an arrangement of said first test points on said IC wafer, and having means for grounding said second test points;
• employing said interconnect structure to interconnect each of said second test points with a separate one of said ports;
• and
• programming said IC tester to measure signal path resistances between said ports and the grounded second test points.