Semiconductor devices and their manufacture
AssigneeKoninklijke Philips Electronics N.V.
InventorJohn R. Cutter
Life of this patent
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AssigneeKoninklijke Philips Electronics N.V.
InventorJohn R. Cutter
Estimating the term…
Thermal cycling can lead to damaging stress at the upper surface of a semiconductor device chip (10) encapsulated in synthetic resin material (100), particularly in the case of power devices that include an IC. The invention provides a thick ductile layer pattern (50) of, for example, aluminium over most of the top surface of the insulating over-layer (40) of the chip (10). Electrically-isolated parts (50a, 50b, 50c, 50d etc.) of this ductile covering are individually connected to respective underlying conductive areas so as to reduce charging effects across the insulating over-layer (40). A sufficient spacing Z1 is present between these isolated parts (50a, 50b, 50c, 50d etc.) to avoid short circuits as a result of deformation by shearing and smearing during thermal cycling of the device. The ductile metal layer pattern (50) reduces stress between the insulating material (40) and the plastic material (100), but it can be both easily and cheaply applied in device manufacture before dividing the wafer into individual chips.
A semiconductor device comprising a semiconductor chip (10) encapsulated in an envelope of synthetic resin material (100), wherein an insulating layer (20) is present at one surface of the chip (10), a pattern (30) of conductive connections (31-39) is present on the insulating layer (20) and at windows (21) in the insulating layer, an over-layer (40) of substantially brittle insulating material is present on the pattern (30) of conductive connections, and a layer pattern (50) is formed of ductile metal to cover at least most of the surface area of the over-layer (40) of insulating material to provide an interface with the synthetic resin material (100) that reduces stress between the insulating material and the synthetic resin material during thermal cycling of the semiconductor device, and wherein the ductile metal layer pattern (50) comprises distinct parts (50a, 50b, 50c, 50d, etc.) that are electrically isolated and spaced from each other on the over-layer (40), the ductile metal of layer pattern (50) is sufficiently ductile as to deform laterally on the over-layer (40) during thermal cycling of the semiconductor device, and the spacing (21) of the electrically-isolated parts (50a, 50b, 50c, 50d, etc.) is sufficient to avoid a short circuit between the electrically-isolated parts as a result of the lateral deformation.
Dependencies are inferred from the claim text.