# US 6,724,087 B1 · Laminated conductive lines and methods of forming the same

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- Number: US 6,724,087 B1
- Document ID: US6724087B1
- Status: Granted
- Kind: B1
- Application number: 10/331,682
- Filed: 2002-12-30
- Granted: 2004-04-20
- Earliest claimed: 2002-07-31
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Matthew S. Buynoski; Paul R. Besser; Sergey D. Lopatin; Lu You
- Web page: https://patentgrep.com/patent/US6724087B1

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at least one interconnect layer, the interconnect layer including a number of conductive lines. Each of the conductive lines includes a first thin barrier layer, a first thin copper layer, a second thin barrier layer and a second thin copper layer. The layered or laminated structure can reduce unconstrained void formation.

## Claims

### Claim 1

An integrated circuit, the integrated circuit comprising at least one interconnect layer, the interconnect layer including a plurality of conductive lines, each of the conductive lines comprising at least three pairs of a first layer containing copper and a second layer containing a barrier material.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein each of the conductive lines is disposed in a trench in a dielectric material.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein at least one of the conductive lines extends into a second trench to form a conductive via, the pairs having a V-shaped or U-shaped cross-sectional area at a point where the pairs extends into the second trench.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the second layer is beneath the first layer and the first layer of an uppermost pair is covered by a barrier layer.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, wherein the barrier material in the second layer comprises tantalum.

### Claim 6 (depends on 4)

The integrated circuit of claim 4, wherein the barrier layer covering the uppermost pair is insulative and the barrier material in the second layer is conductive.

### Claim 7 (depends on 1)

The integrated of claim 1, wherein the trench includes a first side and a second side, wherein one of the pairs has a first portion parallel to a bottom of the trench and a second portion parallel to the first side or the second side.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, wherein the first portion and the second portion are substantially perpendicular.

### Claim 9

A laminated conductive line for an interconnect layer of an integrated circuit, the laminated conductive line comprising:
a first barrier layer above a bottom of a dielectric trench;
a first copper layer above and in contact with the first barrier layer;
a second barrier layer above and in contact with the first copper layer;
a second copper layer above and in contact with the second barrier layer;
a third barrier layer above and in contact with the second copper layer; and
a third copper layer above and in contact with the third barrier layer;
whereby the conductive line includes three copper layers and three barrier layers.

### Claim 10 (depends on 9)

The laminated conductive line of claim 9, further comprising a fourth barrier layer above and in contact with the third copper layer.

### Claim 11 (depends on 9)

The laminated conductive line of claim 9, wherein the trench includes a via trench, the first barrier layer, the fist copper layer, the second barrier layer and the second copper layer extending into the via trench.

### Claim 12 (depends on 11)

The laminated conductive line of claim 11, wherein portions of the first barrier layer, the first copper layer, the second barrier layer and the second copper layer extending into the via trench have a U-shaped or V-shaped cross-sectional area.

### Claim 13 (depends on 9)

The laminated conductive line of claim 9, wherein the first barrier layer and the second barrier layer are tantalum layers.

### Claim 14 (depends on 9)

The laminated conductive line of claim 9, wherein the first barrier layer and the second barrier layer are different materials.

### Claim 15 (depends on 9)

The laminated conductive line of claim 9, wherein the trench includes a first side and a second side, wherein the first barrier layer, the first copper layer, the second barrier layer and the second copper layer have a first portion parallel to a bottom of the trench and a second portion parallel to the first side or the second side.

### Claim 16

An integrated circuit having a plurality of conductive lines, the integrated circuit comprising:
a trench provided in a dielectric material; and
at least a portion of a conductive line provided in the trench, the conductive line comprising:
a first barrier metal layer;
a first layer comprising copper provided in contact with the first barrier metal layer;
a second barrier metal layer provided in contact with the first copper layer;
a second layer comprising copper provided in contact with the second barrier metal layer;
a third barrier metal layer provided in contact with the second layer comprising copper; and
a third layer comprising copper provided in contact with the third barrier metal layer.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein at least one of the first barrier metal and the second barrier metal comprise tantalum.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, further comprising a fourth barrier metal layer provided in contact with the third layer comprising copper.

### Claim 19 (depends on 1)

The integrated circuit of claim 1, wherein at least one of at least three pairs includes a layer containing copper that also comprises at least one of zinc, calcium, chromium, zirconium, and hafnium.

### Claim 20 (depends on 1)

The integrated circuit of claim 1, wherein at least one of at least three pairs includes a layer containing copper that also comprises at least one of lanthanum, barium, strontium, cadmium, cobalt, and nickel.

### Claim 21 (depends on 9)

The laminated conductive line of claim 9, wherein at least one of the copper layers comprises a copper alloy comprising at least one of zinc, calcium, chromium, zirconium, hafnium, lanthanum, barium, strontium, cadmium, cobalt, and nickel.

### Claim 22 (depends on 9)

The laminated conductive line of claim 9, wherein at least one of the copper layers comprises a copper alloy comprising at least one of zinc, calcium, chromium, zirconium, cobalt, and nickel.

### Claim 23 (depends on 16)

The integrated circuit of claim 16, wherein at least one of the layers comprising copper further comprises one of zinc, calcium, chromium, zirconium, hafnium, lanthanum, barium, strontium, cadmium, cobalt, and nickel.

### Claim 24 (depends on 16)

The integrated circuit of claim 16, wherein at least one of the layers comprising copper further comprises at least two elements selected from zinc, calcium, chromium, zirconium, hafnium, lanthanum, barium, strontium, cadmium, cobalt, and nickel.