# US 6,724,086 B1 · Hydrogenated oxidized silicon carbon material > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,086 B1 - Document ID: US6724086B1 - Status: Granted - Kind: B1 - Application number: 09/603,256 - Filed: 2000-06-23 - Granted: 2004-04-20 - Earliest claimed: 1998-06-29 - Assignees: International Business Machines Corporation - Inventors: Alfred Grill; Christopher Vincent Jahnes; Vishnubhai Vitthalbhai Patel; Laurent Claude Perraud - Web page: https://patentgrep.com/patent/US6724086B1 ## CPC - H10W 20/075: {of multilayered thin functional dielectric layers} - C23C 16/325: {Silicon carbide} - H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD} - H10P 14/6548: {by forming intermediate materials, e.g. capping layers or diffusion barriers} - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 20/48: Insulating materials thereof - H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses - H10W 74/476: {Organic materials comprising silicon} - H10P 14/6336: {in the presence of a plasma [PECVD]} - H10P 14/6506: {Formation of intermediate materials} - H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)} - H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane} - H10P 14/6686: {the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane} - H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H} - H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC} - H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers} - Y10T 428/30: Self-sustaining carbon mass or layer with impregnant or other layer - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred. ## Claims ### Claim 1 An electronic structure having layers of insulating material as intralevel or interlevel dielectrics in a wiring structure comprising: a pre-processed semiconducting substrate having a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material selected from the group consisting essentially of SiCOH and SiCH, said second layer of insulating material optionally contain at least one element selected from the group consisting of F, N and Ge, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal, and a second region of conductor being in electrical communication with said first region of conductor and being embedded in a third layer of insulating material selected from the group consisting essentially of SiCOH and SiCH, said third layer of insulating material optionally contain at least one element selected from the group consisting of F, N and Ge, said third layer of insulating material being in intimate contact with said second layer of insulating material. ### Claim 2 (depends on 1) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 1 further comprising a dielectric cap layer situated in-between said second layer of insulating material and said third layer of insulating material. ### Claim 3 (depends on 2) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 2, wherein said dielectric cap layer being formed of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxinitride, refractory metal silicon nitride with the refractory metal being Ta, Zr, Hf or W, silicon carbide, silicon carbo-oxide, their hydrogen-containing compounds and modified SiCOH. ### Claim 4 (depends on 1) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 1 further comprising: a first dielectric cap layer between said second layer of insulating material and said third layer of insulating material, and a second dielectric cap layer on top of said third layer of insulating material. ### Claim 5 (depends on 4) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 4, wherein said first and said second dielectric cap layers are formed of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxinitride, refractory metal silicon nitride with the refractory metal being Ta, Zr, Hf or W, silicon carbo-oxide, their hydrogen-containing compounds and modified SiCOH. ### Claim 6 (depends on 1) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 1, wherein said first layer of insulating material is silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or other doped varieties of these materials. ### Claim 7 (depends on 1) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 1, further comprising: a diffusion barrier layer of a dielectric material deposited on at least one of said second layer of insulating material and said third layer of insulating material. ### Claim 8 (depends on 1) The electronic structure having layers of insulating material as an intralevel or interlevel dielectrics in the wiring structure according to claim 1 further comprising: a dielectric reactive ion etching (RIE) hard mask/polish stop layer on top of said second layer of insulating material, and a dielectric diffusion barrier layer on top of said RIE hard mask/polish stop layer. ### Claim 9 (depends on 1) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 1 further comprising: a first dielectric RIE hard mask/polish stop layer on top of said second layer of insulating material, a first dielectric diffusion barrier layer on top of said first dielectric RIE hard mask/polish stop layer, a second dielectric RIE hard mask/polish stop layer on top of said third layer of insulating material, and a second dielectric diffusion barrier layer on top of said second dielectric RIE hard mask/polish stop layer. ### Claim 10 (depends on 9) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 9 further comprising a dielectric cap layer between an interlevel dielectric of SiCOH or SiCH and an intralevel dielectric of SiCOH or SiCH. ### Claim 11 An electronic structure having layers of insulating material as intralevel or interlevel dielectrics in a wiring structure comprising: a pre-processed semiconducting substrate having a first region of metal embedded in a first layer of insulating material, and at least one first region of conductor embedded in at least one second layer of insulating material selected from the group consisting essentially of SiCOH or and SiCH, said at least one second layer of insulating material optionally contains at least one element selected from the group consisting of F, N and Ge, one of said at least one second layer of insulating material being in intimate contact with said first layer of insulating material, one of said at least one first region of conductor being in electrical communication with said first region of metal. ### Claim 12 (depends on 11) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 11 further comprising a dielectric cap layer situated in-between each of said at least one second layer of insulating material. ### Claim 13 (depends on 12) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 12, wherein said dielectric cap layer being formed of a selected material selected from the group consisting of silicon oxide, silicon nitride, silicon oxinitride, refractory metal silicon nitride with the refractory metal being Ta, Zr, Hf or W, silicon carbide, silicon carbo-oxide, their hydrogen-containing compounds and modified SiCOH. ### Claim 14 (depends on 11) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 11 further comprising: a first dielectric cap layer between each of said at least one second layer of insulating material, and a second dielectric cap layer on top of said topmost second layer of insulating material. ### Claim 15 (depends on 14) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 14, wherein said first and said second dielectric cap layers are formed of SiCOH, SiCH or modified SiCOH. ### Claim 16 An electronic structure having layers of insulating material as intralevel or interlevel dielectrics in a wiring structure comprising: a pre-processed semiconducting substrate having a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal, a second region of conductor being in electrical communication with said first region of conductor and being embedded in a third layer of insulating material, said third layer of insulating material being in intimate contact with said second layer of insulating material, a first dielectric cap layer between said second layer of insulating material and said third layer of insulating material, and a second dielectric cap layer on top of said third layer of insulating material wherein said first and said second dielectric cap layers are formed of a material selected from the group consisting essentially of SiCOH and SiCH, said first and second dielectric cap layers optionally contain at least one element selected from the group consisting of F, N and Ge. ### Claim 17 An electronic structure having layers of insulating material as intralevel or interlevel dielectrics in a wiring structure comprising: a pre-processed semiconducting substrate having a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal, a second region of conductor being in electrical communication with said first region of conductor and being embedded in a third layer of insulating material, said third layer of insulating material being in intimate contact with said second layer of insulating material, and a diffusion barrier layer formed of a material selected from the group consisting essentially of SiCOH and SiCH deposited on at least one of said second layer and said third layer of insulating material, said diffusion barrier layer optionally contain at least one element selected from the group consisting of F, N and Ge. ### Claim 18 An electronic structure having layers of insulating material as intralevel or interlevel dielectrics in a wiring structure comprising: a pre-processed semiconducting substrate having a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal, a second region of conductor being in electrical communication with said first region of conductor and being embedded in a third layer of insulating material, said third layer of insulating material being in intimate contact with said second layer of insulating material, a reactive ion etching (RIE) hard mask/polish stop layer on top of said second layer of insulating material, and a diffusion barrier layer on top of said RIE hard mask/polish stop layer, wherein said RIE hard mask/polish stop layer and said diffusion barrier layer are formed of a material selected from the group consisting essentially of SiCOH and SiCH said RIE hard mask/polish stop layer and said diffusion barrier layer optionally contain at least one element selected from the group consisting of F, N and Ge. ### Claim 19 An electronic structure having layers of insulating material as intralevel or interlevel dielectrics in a wiring structure comprising: a pre-processed semiconducting substrate having a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal, a second region of conductor embedded in said second layer of insulating material, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal, a third region of conductor being in electrical communication with said first region of conductor and being embedded in a third layer of insulating material, said third layer of insulating material being in intimate contact with said second layer of insulating material, a first RIE hard mask/polish stop layer on top of said second layer of insulating material, a diffusion barrier layer on top of said first RIE hard mask/polish stop layer, a second RIE hard mask/polish stop layer on top of said third layer of insulating material, and a second diffusion barrier layer on top of said second RIE hard mask/polish stop layer, wherein said RIE hard mask/polish stop layers and said diffusion barrier layers are formed of a material selected from the group consisting essentially of SiCOH and SiCH. ### Claim 20 (depends on 19) The electronic structure having layers of insulating material as intralevel or interlevel dielectrics in the wiring structure according to claim 19 further comprising a dielectric cap layer formed of a material selected from the group consisting essentially of SiCOH and SiCH situated between an interlevel dielectric layer and an intralevel dielectric layer, said dielectric cap layer optionally contain at least one element selected from the group consisting of F, N and Ge.