Stack semiconductor chip package and lead frame

A stack semiconductor chip package comprising:

• a plurality of stacked semiconductor chips;
• and
• a lead frame;
• the lead frame comprising:
• a plurality of lead groups, each lead group of the plurality to interface a respective one of the semiconductor chips, and
• a plurality of external connection terminals for electrically interconnecting an external device;
• each of the plurality of semiconductor chips comprising:
• an active surface, and
• electrode pads on and within a central region of the active surface;
• each lead group of the plurality of lead groups attached to the active surface of its associated semiconductor chip, each of the lead groups comprising common and independent leads;
• the common leads and the common electrode pads to route address and control signals for the semiconductor chips;
• the independent leads and the independent electrode pads to route data signals for the semiconductor chips;
• at least one common lead of each of the respective lead groups interconnected to an identical external connection terminal of the plurality of external connection terminals;
• opposite facing semiconductor chips of the plurality of stacked semiconductor chips disposed in substantially symmetrical relationship to each other relative to the common leads.

A lead frame to interface at least first and second semiconductor chips in a semiconductor stack package, the lead frame comprising:

• a first lead group to interface the first chip;
• a second lead group to interface the second chip;
• and
• a plurality of outer leads to electrically connect the first and second chips to an external device;
• the first and second lead groups comprising common leads to route address signals and control signals to and from the first and second chips;
• the first and second lead groups further comprising independent leads to route data signals to and from the first and second chips;
• the independent leads of the first lead group and the independent leads of the second lead group disposed in symmetric relationship to each other about the common leads of the first and second lead groups.

A semiconductor device comprising:

• a first semiconductor chip;
• a second semiconductor chip over the first semiconductor chip;
• and
• a lead frame to electrically interface the first and second semiconductor chips to an external device;
• the lead frame comprising:
• a first group of leads to connect electrode pads of the first semiconductor chip, and
• a second group of leads to connect electrode pads of the second semiconductor chip;
• the first group comprising common leads to route address and control signals between the first semiconductor chip and the external device;
• the second group comprising common leads to route address and control signals between the second semiconductor chip and the external device;
• at least one of the common leads of the first group and a respective one of the common leads of the second group interconnected for coupling to a common external connection terminal;
• the first group further comprising independent leads to route data to and from the first semiconductor chip;
• and
• the second group further comprising independent leads to route data to and from the second semiconductor chip;
• the independent leads of the first group separate from the independent leads of the second group.