# US 6,724,065 B2 · Static random access memory and semiconductor device using MOS transistors having channel region electrically connected with gate

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- Number: US 6,724,065 B2
- Document ID: US6724065B2
- Status: Granted
- Kind: B2
- Application number: 09/412,328
- Filed: 1999-10-05
- Published: 2003-06-05
- Granted: 2004-04-20
- Earliest claimed: 1998-10-05
- Assignees: Sharp Kabushiki Kaisha
- Inventors: Yuichi Sato
- Web page: https://patentgrep.com/patent/US6724065B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/412: using field-effect transistors only
- Y10S 257/903: FET configuration adapted for use as static memory cell
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

In an SRAM, memory cells are each constructed of four NMOS transistors and two PMOS transistors 25 and 26. The four NMOS transistors are each constructed of DTMOS in which the channel region is electrically connected to the gate. In each NMOS transistor, a threshold voltage Vth is lower in an ON stage than in an OFF stage. The threshold voltage Vth in the OFF stage is equivalent to that of an ordinary NMOS transistor in which the channel region is not electrically connected to the gate. Read and write circuits of the SRAM also include MOS transistors formed of DTMOS in which the channel region is electrically connected to the gate.

## Claims

### Claim 1

A static random access memory, wherein memory cells of the static random access memory each includes:
N-type MOS transistors each having a channel-forming semiconductor region and a gate electrically connected with each other; and
P-type MOS transistors each having a channel-forming semiconductor region electrically connected with a power source,
wherein the channel-forming semiconductor regions of the P-type MOS transistors are formed of a same deep N-type well so that these channel-forming semiconductor regions are electrically connected to each other, and the channel-forming semiconductor regions of the N-type MOS transistors are formed of shallow P-type wells formed in the deep N-type well,
wherein trenches are individually provided between the channel-forming semiconductor regions of the P-type and N-type MOS transistors, said trenches being deeper than the shallow P-type wells, but shallower than the deep N-type well.

### Claim 2 (depends on 1)

A static random access memory as claimed in claim 1, wherein said P-type MOS transistor has a gate oxide him larger in thickness than said N-type MOS semiconductor transistor.

### Claim 3 (depends on 1)

A static random access memory as claimed in claim 1, comprising write circuit means that include:
MOS transistors each having a channel-forming semiconductor region and a gate electrically connected with each other.

### Claim 4 (depends on 3)

A static random access memory as claimed in claim 3, wherein said MOS transistors of the write circuit means include N-type MOS transistors which serve to make a bit line and an inverted bit line have a high-level electric potential, respectively.

### Claim 5 (depends on 1)

A static random access memory as claimed in claim 1, comprising read circuit means that include MOS transistors each having a channel-forming semiconductor region and a gate electrically connected with each other.