# US 6,724,044 B2 · MOSFET device having geometry that permits frequent body contact > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,044 B2 - Document ID: US6724044B2 - Status: Granted - Kind: B2 - Application number: 10/142,674 - Filed: 2002-05-10 - Published: 2003-11-13 - Granted: 2004-04-20 - Earliest claimed: 2002-05-10 - Assignees: General Semiconductor, Inc. - Inventors: Richard A. Blanchard - Web page: https://patentgrep.com/patent/US6724044B2 ## CPC - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 62/378: {Contact regions to the substrate regions} - H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A MOSFET device design is provided that effectively addresses the problems arising from the parasitic bipolar transistor that is intrinsic to the device. The MOSFET device comprises: (a) a body region; (b) a plurality of body contact regions; (c) a plurality of source regions; (d) a plurality of drain regions; and (d) a gate region. In plan view, the source regions and the drain regions are arranged in orthogonal rows and columns, and at least a portion of the body contact regions are bordered by four of the source and drain regions, preferably two source regions and two drain regions. ## Claims ### Claim 1 A MOSFET device comprising: a semiconductor region of first conductivity type having an upper surface; a plurality or source regions of a second conductivity type formed within an upper portion of said semiconductor region adjacent said upper surface; a plurality of drain regions of said second conductivity type formed within an upper portion of said semiconductor region adjacent said upper surface; a plurality of body contact regions of said first conductivity type formed within an upper portion of said semiconductor region adjacent said upper surface; said body contact regions having a net doping concentration that is higher than that of said semiconductor region; and a gate region disposed over said upper surface of said semiconductor region, said gate region comprising (a) a gate electrode region, wherein said gate electrode region comprises a continuous region with openings therein for said plurality of source regions, said plurality of drain regions and said plurality of body contact regions, and (b) a gate dielectric layer disposed between said gate electrode region and said semiconductor region, wherein, when viewed from above said upper surface, said source regions and said drain regions are arranged in orthogonal rows and columns, and wherein at least a portion of said body contact regions are bordered by four of said source and drain regions, and further wherein the body contact regions inside a perimeter of said plurality of source regions or said plurality of drain regions are completely surrounded by said gate electrode region. ### Claim 2 (depends on 1) The MOSFET device of claim 1 wherein said first conductivity type is P-type conductivity and said second conductivity type is N-type conductivity. ### Claim 3 (depends on 1) The MOSFET device of claim 1 wherein said semiconductor region is a silicon semiconductor region. ### Claim 4 (depends on 1) The MOSFET device of claim 1 wherein said gate electrode region is a doped polysilicon electrode region. ### Claim 5 (depends on 1) The MOSFET device of claim 1 wherein said gate dielectric is silicon dioxide. ### Claim 6 (depends on 1) The MOSFET device of claim 1 wherein, when viewed from above said upper surface, said source regions and said drain regions are in the shape of octagons. ### Claim 7 (depends on 6) The MOSFET device of claim 6 wherein said octagons are regular octagons. ### Claim 8 (depends on 6) The MOSFET device of claim 6 wherein said octagons are elongated octagons having two planes of symmetry. ### Claim 9 (depends on 6) The MOSFET device of claim 6 wherein, when viewed from above said upper surface, said body contact regions are in the shape of octagons. ### Claim 10 (depends on 6) The MOSFET device of claim 6 wherein, when viewed from above said upper surface, said body contact regions are in the shape of squares or diamonds. ### Claim 11 (depends on 1) The MOSFET device of claim 1, wherein each source region is provided with four adjacent body contact regions. ### Claim 12 (depends on 1) The MOSFET device of claim 1, wherein each source region is provided with two adjacent body contact regions. ### Claim 13 (depends on 1) The MOSFET device of claim 1, wherein each source region is provided with one adjacent body contact region. ### Claim 14 (depends on 1) The MOSFET device of claim 1, wherein said portion of said body contact regions are bordered by two source regions and two drain regions. ### Claim 15 (depends on 1) The MOSFET device of claim 1, wherein said source regions and said drain regions are provided in an alternating arrangement within said orthogonal rows and columns. ### Claim 16 (depends on 1) The MOSFET device of claim 1, wherein a multilayer interconnect structure is provided over said MOSFET device. ### Claim 17 A MOSFET semiconductor device comprising: (a) a body region; (b) a plurality of body contact regions; (c) a plurality of source regions; (d) a plurality of drain regions; and (d) a gate region, said gate region comprising a continuous sheet having openings for said plurality of body contact regions, said plurality or source regions and said plurality of drain regions, wherein, in plan view, said source regions and said drain regions are arranged in orthogonal rows and columns, and wherein at least a portion of said body contact regions are bordered by four of said source and drain regions, and wherein the body contact regions inside the perimeter rows of said plurality of source regions and said plurality of drain regions are completely surrounded by said gate region. ### Claim 18 (depends on 17) The MOSFET device of claim 17 wherein, in plan view, said source regions and said drain regions are in the shape of octagons. ### Claim 19 (depends on 18) The MOSFET device of claim 18 wherein said octagons are regular octagons. ### Claim 20 (depends on 18) The MOSFET device of claim 18 wherein said octagons are elongated octagons having two planes of symmetry. ### Claim 21 (depends on 17) The MOSFET device of claim 17 wherein, in plan view, said body contact regions are in the shape of octagons. ### Claim 22 (depends on 17) The MOSFET device of claim 17 wherein, in plan view, said body contact regions are in the shape of squares or diamonds. ### Claim 23 (depends on 17) The MOSFET device of claim 17, wherein said source regions and said drain regions are provided in an alternating arrangement within said orthogonal rows and columns. ### Claim 24 (depends on 17) The MOSFET device of claim 17, wherein said portion of said body contact regions are bordered by two source regions and two drain regions. ### Claim 25 (depends on 17) The MOSFET device of claim 17, wherein each source region is provided with four adjacent body contact regions. ### Claim 26 (depends on 17) The MOSFET device of claim 17, wherein each source region is provided with two adjacent body contact regions. ### Claim 27 (depends on 17) The MOSFET device of claim 17, wherein each source region is provided with one adjacent body contact region.