# US 6,724,041 B2 · Method of making a high-voltage transistor with buried conduction regions

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- Number: US 6,724,041 B2
- Document ID: US6724041B2
- Status: Granted
- Kind: B2
- Application number: 10/277,849
- Filed: 2002-10-21
- Published: 2003-03-06
- Granted: 2004-04-20
- Earliest claimed: 1996-11-05
- Assignees: Power Integrations, Inc.
- Inventors: Vladimir Rumennik; Donald R. Disney; Janardhanan S. Ajit
- Web page: https://patentgrep.com/patent/US6724041B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/028: {of double-diffused metal oxide semiconductor [DMOS] FETs}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/64: Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/156: {Drain regions of DMOS transistors}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10P 30/22: using masks
- H10P 34/00: Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
- H10D 30/615: {comprising a MOS gate electrode and at least one non-MOS gate electrode}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 64/111: {Field plates}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

## Claims

### Claim 1

A high voltage field-effect transistor (HVFET) comprising:
a substrate of a first conductivity type;
a source diffusion region of a second conductivity type opposite to the first conductivity type disposed in the substrate, the source diffusion region having a source fingertip area;
a first region of the second conductivity type disposed in the substrate inter-digitated with the source diffusion region, the first region being separated in a lateral direction from the source diffusion region by a channel region;
a drain diffusion region of the second conductivity type disposed in the first region;
a drain electrode electrically connected to the drain diffusion region;
a buffer region of the substrate separating the source diffusion region from the first region adjacent the source fingertip area, the buffer region being substantially wider than the channel region, the first region extending laterally beyond the drain electrode adjacent the buffer region;
an insulated gate disposed above the channel region;
a source electrode electrically connected to the source diffusion region;
a buried region of the first conductivity type disposed within the first region, a first conduction channel being formed above the buried region and a second conduction channel being formed below the buried region.

### Claim 2 (depends on 1)

The HVFET according to claim 1 wherein the drain electrode has a drain field plate that overlaps a portion of the first region.

### Claim 3 (depends on 2)

The HVFET according to claim 2 wherein the drain electrode includes a portion having a larger extension over the drain fingertips areas, the portion extending a lateral distance past the drain field plate.

### Claim 4 (depends on 1)

The HVFET according to claim 1 wherein the source electrode includes a source field plate that extends over the insulated gate.

### Claim 5 (depends on 1)

The HVFET according to claim 1 wherein the first and second conductivity types are n-type and p-type, respectively.

### Claim 6 (depends on 1)

The HVFET according to claim 1 wherein the buried region is coupled to the substrate.

### Claim 7

A high voltage field-effect transistor (HVFET) comprising:
a substrate of a first conductivity type;
a source diffusion region of a second conductivity type opposite to the first conductivity type disposed in the substrate, the source diffusion region having a source fingertip area;
a first region of the second conductivity type disposed in the substrate inter-digitated with the source diffusion region, the first region being separated in a lateral direction from the source diffusion region by a channel region, the first region being separated from the source fingertip area by a buffer region that is substantially wider than the channel region;
a drain diffusion region of the second conductivity type disposed in the first region;
a drain electrode electrically connected to the drain diffusion region;
insulated gate disposed above the channel region;
a source electrode electrically connected to the source diffusion region;
a buried region of the first conductivity type disposed within the first region, the buried region forming JFET channels within the first region, one JFET channel being formed above the buried region with a doped impurity concentration of approximately 1×1012/cm2 or greater and another JFET channel below the buried region.

### Claim 8 (depends on 7)

The HVFET according to claim 7 wherein the buried region is spaced-apart from the drain diffusion region.

### Claim 9 (depends on 7)

The HVFET according to claim 7 wherein the drain electrode has a drain field plate that overlaps a portion of the first region.

### Claim 10 (depends on 9)

The HVFET according to claim 9 wherein the drain electrode includes a portion having a larger extension over the drain fingertips areas, the portion extending a lateral distance past the drain field plate.

### Claim 11 (depends on 7)

The HVFET according to claim 7 wherein the source electrode includes a source field plate that extends over the insulated gate.

### Claim 12 (depends on 7)

The HVFET according to claim 7, wherein the first and second conductivity types are n-type and p-type, respectively.

### Claim 13 (depends on 7)

The HVFET according to claim 7, wherein the buried region is coupled to the substrate.

### Claim 14

A high voltage field-effect transistor (HVFET) comprising:
a substrate of a first conductivity type;
a source diffusion region of a second conductivity type opposite to the first conductivity type disposed in the substrate, the source diffusion region having a source fingertip area;
a first region of the second conductivity type disposed in the substrate inter-digitated with the source diffusion region, the first region being separated in a lateral direction from the source diffusion region by a channel region;
a drain diffusion region of the second conductivity type disposed in the first region;
a drain electrode electrically connected to the drain diffusion region;
a buffer region of the substrate separating the source diffusion region from the first region adjacent the source fingertip area, the buffer region being substantially wider than the channel region;
an insulated gate disposed above the channel region;
a source electrode electrically connected to the source diffusion region;
a buried region of the first conductivity type disposed within the first region, a first conduction channel being formed above the buried region and a second conduction channel being formed below the buried region, the first conduction channel being approximately 0.5 to 1.5 microns thick.

### Claim 15 (depends on 14)

The HVFET according to claim 14, wherein the first and second conductivity types are n-type and p-type, respectively.

### Claim 16 (depends on 14)

The HVFET according to claim 14, wherein the buried region is coupled to the substrate.

### Claim 17 (depends on 14)

The HVFET according to claim 14 wherein the buried region is spaced-apart from the drain diffusion region.

### Claim 18 (depends on 14)

The HVFET according to claim 14 wherein the drain electrode has a drain field plate that overlaps a portion of the first region.

### Claim 19 (depends on 18)

The HVFET according to claim 18 wherein the drain electrode includes a portion having a larger extension over the drain fingertips areas, the portion extending a lateral distance past the drain field plate.

### Claim 20 (depends on 14)

The HVFET according to claim 14 wherein the source electrode includes a source field plate that extends over the insulated gate.