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US 6,724,038 B2Granted
Memory element for a semiconductor memory device
AssigneeInfineon Technologies AG
InventorThomas Mikolajick
Life of this patent
Estimating the term…
Abstract
A memory element includes a number of material areas isolated from one another to form at least one area with changed electrical and/or magnetic characteristics in an isolation area, which material areas have or form free charge carriers. An information unit can correspondingly be written to, deleted, and/or read from by influencing the material areas by applying an electrical potential to line devices that are provided in areas.
Claims26
A memory element for a semiconductor memory device, comprising:
- a semiconductor substrate of a first conductance type having:
- a surface area;
- an intermediate area;
- and
- a number of line devices formed one of in said semiconductor substrate and in said surface area, said line devices substantially electrically insulated from one another in pairs and at least partially formed and disposed physically separated from one another in pairs by said intermediate area;
- an isolation area of an substantially electrically insulating material, said isolation area mechanically and electrically contacted with:
- said intermediate area;
- and
- each of said line devices at a respective overlap area of each of said line devices;
- said isolation area having a number of material areas isolated from one another to form at least one area with at least one of changed electrical characteristics and changed magnetic characteristics in said isolation area, at least one of:
- each of said material areas having free charge carriers;
- and
- each of said material areas being able to have free charge carriers formed therein;
- and
- said line devices and said isolation area at least temporarily forming said at least one area when an electrical potential distribution is applied to said line devices and to said isolation area in said isolation area in accordance with an information unit that is to be stored.
12 more elements
A memory element for a semiconductor memory device, comprising:
- a semiconductor substrate of a first conductance type having:
- a surface area;
- an intermediate area;
- and
- a number of line devices formed one of in said semiconductor substrate and in said surface area, said line devices substantially electrically insulated from one another in pairs and at least partially formed and disposed physically separated from one another in pairs by said intermediate area;
- an isolation area of an substantially electrically insulating material, said isolation area mechanically and electrically contacted with:
- said intermediate area;
- and
- each of said line devices at a respective overlap area of each of said line devices;
- said isolation area having a number of material areas isolated from one another to form at least one area with at least one of changed electrical characteristics and changed magnetic characteristics in said isolation area, at least one of:
- each of said material areas having free charge carriers;
- and
- each of said material areas being able to have free charge carriers formed therein;
- and
- said overlap areas and said isolation area at least temporarily forming said at least one area when an electrical potential distribution is applied to said overlap areas and to said isolation area in said isolation area in accordance with an information unit that is to be stored.
12 more elements
A memory element for a multibit memory cell, comprising:
- a semiconductor substrate of a first conductance type having:
- a surface area;
- an intermediate area;
- and
- a number of line devices formed one of in said semiconductor substrate and in said surface area, said line devices substantially electrically insulated from one another in pairs and at least partially formed and disposed physically separated from one another in pairs by said intermediate area;
- an isolation area of an substantially electrically insulating material, said isolation area mechanically and electrically contacted with:
- said intermediate area;
- and
- each of said line devices at a respective overlap area of each of said line devices;
- said isolation area having a number of material areas isolated from one another to form at least one area with at least one of changed electrical characteristics and changed magnetic characteristics in said isolation area, at least one of:
- each of said material areas having free charge carriers;
- and
- each of said material areas being able to have free charge carriers formed therein;
- and
- said overlap areas and said isolation area at least temporarily forming said at least one area when an electrical potential distribution is applied to said overlap areas and to said isolation area in said isolation area in accordance with an information unit that is to be stored.
12 more elements
A memory element for a multibit memory cell, comprising:
- a semiconductor substrate of a first conductance type having:
- a surface area;
- an intermediate area;
- and
- a number of line devices formed one of in said semiconductor substrate and in said surface area, said line devices substantially electrically insulated from one another in pairs and at least partially formed and disposed physically separated from one another in pairs by said intermediate area;
- an isolation area of an substantially electrically insulating material, said isolation area mechanically and electrically contacted with:
- said intermediate area;
- and
- each of said line devices at a respective overlap area of each of said line devices;
- said isolation area having a number of material areas isolated from one another to form at least one area with at least one of changed electrical characteristics and changed magnetic characteristics in said isolation area, at least one of:
- each of said material areas having free charge carriers;
- and
- each of said material areas being able to have free charge carriers formed therein;
- and
- said line devices and said isolation area at least temporarily forming said at least one area when an electrical potential distribution is applied to said line devices and to said isolation area in said isolation area in accordance with an information unit that is to be stored.
12 more elements
Dependencies are inferred from the claim text.