# US 6,724,037 B2 · Nonvolatile memory and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,037 B2 - Document ID: US6724037B2 - Status: Granted - Kind: B2 - Application number: 09/908,804 - Filed: 2001-07-20 - Published: 2002-02-21 - Granted: 2004-04-20 - Earliest claimed: 2000-07-21 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Shunpei Yamazaki; Jun Koyama; Kiyoshi Kato - Web page: https://patentgrep.com/patent/US6724037B2 ## CPC - H10D 86/40: characterised by multiple TFTs - H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate} - H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon} - H10D 30/6731: {Top-gate only TFTs} - H10D 30/6744: {Monocrystalline silicon} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 86/60: wherein the TFTs are in active matrices - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A nonvolatile memory transistor with multi values being capable of suppressing a short channel effect is provided. In an active region of a memory transistor, stripe-shaped impurity regions (pinning regions) are formed in a channel length direction. The pinning regions suppress the spread of a depletion layer of a drain region, and a short channel effect caused by fine processing. Furthermore, in a memory transistor using pinning regions, by assigning one value or one bit of data to each channel forming region, the memory transistor is allowed to have multi values. More specifically, the present invention has a configuration in which a floating gate electrode is provided on each of a plurality of channel forming regions via a first gate insulating film, and an electric potential can be applied independently to a plurality of pinning regions. ## Claims ### Claim 1 A nonvolatile memory comprising a memory transistor, said memory transistor comprising: a source region, a drain region and an active region using a single crystal semiconductor, said active region comprising: a plurality of impurity regions provided in a stripe shape in a channel length direction, a plurality of intrinsic or substantially intrinsic channel forming regions interposed between the plurality of impurity regions, and wherein the memory transistor stores multi-valued data. ### Claim 2 A nonvolatile memory comprising a memory transistor, said memory transistor comprising: a source region, a drain region and an active region using a single crystal semiconductor; a first gate insulating film over the active region; a plurality of floating gate electrodes; a second gate insulating film; a control gate electrode, said active region comprising: a plurality of impurity regions provided in a stripe shape in a channel length direction, a plurality of intrinsic or substantially intrinsic channel forming regions interposed between the plurality of impurity regions, wherein each of the plurality of floating gate electrodes is provided over each of the plurality of channel forming regions via the first gate insulating film, wherein the control gate electrode is overlapped with the plurality of floating gate electrodes via the second gate insulating film, wherein the memory transistor stores multi-valued data. ### Claim 3 A nonvolatile memory comprising a memory transistor, said memory transistor comprising: a source region, a drain region and an active region using a single crystal semiconductor; a first gate insulating film over the active region; a plurality of floating gate electrodes; a second gate insulating film; a control gate electrode, said active region comprising: a plurality of impurity regions provided in a stripe shape in a channel length direction, a plurality of intrinsic or substantially intrinsic channel forming regions interposed between the plurality of impurity regions, wherein each of the plurality of floating gate electrodes is provided over each of the plurality of channel forming regions via the first gate insulating film, wherein the control gate electrode is overlapped with the plurality of floating gate electrodes via the second gate insulating film, wherein an electric potential of each of the plurality of impurity regions is independently controlled, wherein the memory transistor stores multi-valued data. ### Claim 4 (depends on 2) A memory according to claim 2, wherein each of the plurality of floating gate electrodes is partially overlapped with one of the plurality of impurity regions via the first gate insulating film. ### Claim 5 (depends on 1) A memory according to claim 1, wherein the plurality of impurity regions provided in the active region are formed continuously in at least one of the source region and the drain region. ### Claim 6 (depends on 1) A memory according to claim 1, wherein each of the plurality of impurity regions comprises an element selected from Group 13 or Group 15 of the Periodic Table. ### Claim 7 (depends on 1) A memory according to claim 1, wherein each of the plurality of impurity regions comprises an element selected from Group 13 or Group 15 of the Periodic Table, wherein each of the plurality of impurity regions suppresses a depletion layer spreading from the drain region to the source region. ### Claim 8 (depends on 1) A memory according to claim 1, wherein each of the plurality of impurity regions comprises an element at a concentration in a range of 1×1017 to 5×1020 atoms/cm3. ### Claim 9 (depends on 1) A memory according to claim 1, wherein a channel length of the memory transistor is in a range of 0.01 to 1 μm. ### Claim 10 (depends on 1) A memory according to claim 1, wherein a width of each of the plurality of impurity regions is in a range of 0.01 to 1 μm. ### Claim 11 (depends on 1) A memory according to claim 1, wherein a width of each of the plurality of channel forming regions is in a range of 0.01 to 1 μm. ### Claim 12 (depends on 1) A semiconductor device utilizing the nonvolatile memory of claim 1 as a recording medium. ### Claim 13 (depends on 12) A device according to claim 12, wherein the semiconductor device is a microprocessor. ### Claim 14 (depends on 12) A device according to claim 12, wherein the semiconductor device is one selected from the group consisting of a display, a video camera, a head mount display, a DVD player, a goggle type display, a personal computer, a mobile phone, and a car audio system. ### Claim 15 (depends on 2) A memory according to claim 2, wherein the plurality of impurity regions provided in the active region are formed continuously in at least one of the source region and the drain region. ### Claim 16 (depends on 2) A memory according to claim 2, wherein each of the plurality of impurity regions comprises an element selected from Group 13 or Group 15 of the Periodic Table. ### Claim 17 (depends on 2) A memory according to claim 2, wherein each of the plurality of impurity regions comprises an element selected from Group 13 or Group 15 of the Periodic Table, wherein each of the plurality of impurity regions suppresses a depletion layer spreading from the drain region to the source region. ### Claim 18 (depends on 2) A memory according to claim 2, wherein each of the plurality of impurity regions comprises an element at a concentration in a range of 1×1017 to 5×1020 atoms/cm3. ### Claim 19 (depends on 2) A memory according to claim 2, wherein a channel length of the memory transistor is in a range of 0.01 to 1 μm. ### Claim 20 (depends on 2) A memory according to claim 2, wherein a width of each of the plurality of impurity regions is in a range of 0.01 to 1 μm. ### Claim 21 (depends on 2) A memory according to claim 2, wherein a width of each of the plurality of channel forming regions is in a range of 0.01 to 1 μm. ### Claim 22 (depends on 2) A semiconductor device utilizing the nonvolatile memory of claim 2 as a recording medium. ### Claim 23 (depends on 22) A device according to claim 22, wherein the semiconductor device is a microprocessor. ### Claim 24 (depends on 22) A device according to claim 22, wherein the semiconductor device is one selected from the group consisting of a display, a video camera, a head mount display, a DVD player, a goggle type display, a personal computer, a mobile phone, and a car audio system. ### Claim 25 (depends on 3) A memory according to claim 3, wherein each of the plurality of floating gate electrodes is partially overlapped with one of the plurality of impurity regions via the first gate insulating film. ### Claim 26 (depends on 3) A memory according to claim 3, wherein the plurality of impurity regions provided in the active region are formed continuously in at least one of the source region and the drain region. ### Claim 27 (depends on 3) A memory according to claim 3, wherein each of the plurality of impurity regions comprises an element selected from Group 13 or Group 15 of the Periodic Table. ### Claim 28 (depends on 3) A memory according to claim 3, wherein each of the plurality of impurity regions comprises an element selected from Group 13 or Group 15 of the Periodic Table, wherein each of the plurality of impurity regions suppresses a depletion layer spreading from the drain region to the source region. ### Claim 29 (depends on 3) A memory according to claim 3, wherein each of the plurality of impurity regions comprises an element at a concentration in a range of 1×1017 to 5×1020 atoms/cm3. ### Claim 30 (depends on 3) A memory according to claim 3, wherein a channel length of the memory transistor is in a range of 0.01 to 1 μm. ### Claim 31 (depends on 3) A memory according to claim 3, wherein a width of each of the plurality of impurity regions is in a range of 0.01 to 1 μm. ### Claim 32 (depends on 3) A memory according to claim 3, wherein a width of each of the plurality of channel forming regions is in a range of 0.01 to 1 μm. ### Claim 33 (depends on 3) A semiconductor device utilizing the nonvolatile memory of claim 3 as a recording medium. ### Claim 34 (depends on 33) A device according to claim 33, wherein the semiconductor device is a microprocessor. ### Claim 35 (depends on 33) A device according to claim 33, wherein the semiconductor device is one selected from the group consisting of a display, a video camera, a head mount display, a DVD player, a goggle type display, a personal computer, a mobile phone, and a car audio system.