Multi-bit non-volatile memory cell and method therefor

A memory cell comprising:

• a substrate;
• a first insulator overlying a first portion of the substrate;
• a second insulator overlying a second portion of the substrate;
• a first storage clement overlying the first insulator for storing a first data bit;
• a second storage element overlying the second insulator for storing a second data bit;
• a third insulator overlying the first storage element;
• a fourth insulator overlying the second storage element;
• a fifth insulator having a material different from the first storage element and the second storage element and interposed between the first storage element and the second storage element;
• a control electrode overlying the third insulator, the fourth insulator and the fifth insulator;
• first and second current electrodes formed in the substrate and separated by a channel region;
• and
• a region of net higher impurity concentration from other areas of the channel region and formed in the channel underlying the fifth insulator, the region of net higher impurity concentration limiting a depletion region within the channel when either of the first storage element and the second storage element of the memory cell is read or programmed.

A memory cell comprising:

• a substrate;
• a first insulator overlying a first portion of the substrate;
• a second insulator overlying a second portion of the substrate;
• a first storage element overlying the first insulator for storing a first data bit;
• a second storage element overlying the second insulator for storing a second data bit;
• a third insulator interposed between the first storage element and the second storage element and having a material composition that differs from that of the first storage element and the second storage element to electrically isolate the first storage element from the second storage element;
• a fourth insulator overlying the first storage element, the second storage element and the third insulator;
• a control electrode overlying the fourth insulator;
• a first current electrode and a second current electrode formed in the substrate and separated by a channel region;
• a first region formed within the channel having net lower impurity concentration than a central portion of the channel underlying the third insulator;
• and
• a second region formed within the channel also having net lower impurity concentration than the central portion of the channel underlying the third insulator.

A multiple-bit memory cell comprising:

• a substrate having a first portion and a second portion;
• a first storage element overlying the first portion of the substrate for storing a first data bit in the memory cell;
• a second storage element overlying the second portion of the substrate for storing a second data bit in the memory cell;
• an insulator electrically separating the first storage element from the second storage element, the insulator comprising a material that is different from the first storage element and the second storage element;
• a control electrode overlying the first storage element, the second storage element and the insulator;
• a first current electrode and a second current electrode formed in the substrate, a portion of each of the first current electrode and the second current electrode respectively underlying a portion of the first storage element and the second storage element, the first current electrode and the second current electrode forming a channel region;
• and
• a region within the channel having net higher impurity concentration than other areas of the channel and formed underlying the insulator, the region functioning to restrict a depletion region created when either of the first storage element and the second storage element of the multiple-bit memory cell is read or programmed.