# US 6,724,029 B2 · Twin-cell flash memory structure and method

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- Number: US 6,724,029 B2
- Document ID: US6724029B2
- Status: Granted
- Kind: B2
- Application number: 09/683,831
- Filed: 2002-02-21
- Published: 2003-08-21
- Granted: 2004-04-20
- Earliest claimed: 2002-02-21
- Assignees: International Business Machines Corporation
- Inventors: Louis L. Hsu; Chung H. Lam; Jack A. Mandelman; Carl J. Radens; William R. Tonti
- Web page: https://patentgrep.com/patent/US6724029B2

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.

## Claims

### Claim 1

A pair of programmable memory cells comprising a shared control gate, first and second floating gates having respective gate regions located on respective sides of the control gate, and dielectric structures located between said control gate and respective ones of said gates of said floating gates, wherein said control gate includes portions that lay above said floating gates, and said control gate and said gates of said first and second floating gates are located within a space of a single lithographic square.

### Claim 2 (depends on 1)

The pair of programmable memory cells of claim 1 wherein respective heights of said control gate and said gates of said first and said second floating gate devices are optimize to achieve capacitance coupling therebetween.

### Claim 3 (depends on 1)

The pair of programmable memory cells of claim 1 further comprising a first bitline and a second bitline, wherein said first bitline is borderless to said first floating gate and said second bitline is borderless to said second floating gate.

### Claim 4 (depends on 1)

The pair of programmable memory cells of claim 1 further comprising a wordline interconnected to said control gate.

### Claim 5 (depends on 1)

The pair of programmable memory cells of claim 1 further comprising shallow trench isolation regions, said shallow trench isolation regions being located adjacent to said pair of memory cells.

### Claim 6 (depends on 5)

The pair of programmable memory cells of claim 5 wherein said shallow trench isolation regions are formed self-aligned to bitline diffusion regions that abut said pair of memory cells and edges of said first and second floating gates.

### Claim 7 (depends on 1)

The pair of programmable memory cells of claim 1 further comprising a common reference line that is located beneath an insulated portion of said control gate.

### Claim 8 (depends on 1)

The pair of programmable memory cells of claim 1 wherein said cells are EEPROM memory cells, non-volatile memory cells or flash memory cells.

### Claim 9 (depends on 5)

The pair of programmable memory cells of claim 5 further comprising patterned bitlines formed above said shallow trench isolation regions.

### Claim 10

A pair of programmable memory cells comprising a single control gate, a first floating gate, a second floating gate, a first bitline, and a second bitline, wherein said control gate is self-aligned to said first and second floating gates.

### Claim 11 (depends on 10)

The pair of programmable memory cells of claim 10 wherein said first bitline is borderless to said first floating gate and said second bitline is borderless to said second floating gate.

### Claim 12 (depends on 10)

The pair of programmable memory cells of claim 10 further comprising a wordline connected to said control gate, wherein said first bitline and said second bitline are both borderless to said control gate and said wordline.

### Claim 13 (depends on 10)

The pair of programmable memory cells of claim 10 wherein coupling between said floating gates and said control gate is controllable by heights of said floating gates.

### Claim 14 (depends on 10)

The pair of programmable memory cells of claim 10 further comprising shallow trench isolation regions, said shallow trench isolation regions being located adjacent to said pair of programmable memory cells.

### Claim 15 (depends on 14)

The pair of programmable memory cells of claim 14 wherein said shallow trench isolation regions are formed self-aligned to bitline diffusion regions that abut said pair of memory cells and edges of said first and second floating gates.

### Claim 16 (depends on 10)

The pair of programmable memory cells of claim 10 further comprising a common reference line that is located beneath an insulated portion of said control gate.

### Claim 17 (depends on 10)

The pair of programmable memory cells of claim 10 wherein said cells are EEPROM memory cells, non-volatile memory cells or flash memory cells.

### Claim 18

A layout for a non-volatile memory cell comprising a programmable memory cell comprising a shared control gate, first and second floating gates having respective sate regions located on respective sides of the control gate, and dielectric structures located between said control gate and respective ones of said sates of said floating gates, wherein said control gate includes portions that lay above said floating gates, said shared control gate coupled to a wordline that is borderless to an orthogonal bitline.