Matrix-addressable array of integrated transistor/memory structures

A matrix-addressable array of integrated transistor/memory structures, the array comprising one or more layers of semiconducting material, two or more electrode layers as well as memory material contacting electrodes in said two or more electrode layers, the memory material being a polarizable dielectric material capable of exhibiting hysteresis, particularly a ferroelectric or electret material, the electrodes in said at least two electrode layers in each layer being provided as continuous or interrupted parallel extended structures, said at least one layer of a semiconducting material and said at least two electrode layers forming field-effect transistor structures, the electrodes of a first electrode layer forming the source/drain electrode pairs of said field-effect transistor structures, the electrodes of an adjacent second electrode layer forming the gate electrodes of the field-effect transistor structures, the gate electrodes in any case provided in a substantial orthogonal orientation relative to the electrodes of the first electrode layer, the source and drain electrodes of a single transistor/memory structure being separated by a narrow vertical recess extending therebetween and down to the semiconducting layer, a transistor channel being provided in the semiconducting layer beneath the recess between the source and drain electrodes, the source and drain regions of the transistor structures being provided beneath the source and drain electrodes at either side of the transistor channel the memory material being provided filling the recess between the source and drain electrodes and covering the top surfaces thereof, a gate electrode being provided contacting the memory material whereby the transistor channel being defined with a length L corresponding to the width of the recess and a width W corresponding to the width of the gate electrode, L being a fraction of W, and three memory cells being defined in the memory material respectively between the source electrode and the gate electrode, between the drain electrode and the gate electrode and in the recess between the source and drain electrodes.