Field effect transistor pull-up/load element
AssigneeProgressant Technologies, Inc.
InventorKing Tsu-Jae
Life of this patent
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Abstract
An improved MISFET is disclosed which is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The MISFET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The MISFET channel can be shut off during static operations to further reduce power dissipation, and can also be adapted to operate with negative differential resistance.
Claims9
In a memory cell including at least one first dopant type channel insulated gate field effect transistor (IGFET), the first-channel type IGFET having an IGFET gate terminal, and a first IGFET source/drain terminal coupled to a storage node, the improvement comprising:
- a negative differential resistance field-effect transistor (NDR-FET) element that also has a first dopant-type channel, said NDR FET element including a first NDR FET source/drain terminal connected to a first potential, a second NDR source/drain terminal connected to the storage node, and a third NDR gate terminal connected to a bias voltage;
- wherein the NDR FET element operates as a pull-up device for the memory cell, so that the memory cell is formed with active devices having a common channel dopant type.
In a silicon based memory cell which stores data at a storage node coupled between a high voltage potential source and a low voltage potential source, the improvement comprising:
- a silicon based negative differential resistance (NDR) field effect transistor (FET) configured as a NDR FET load element that is coupled between the storage node of the memory device and the high voltage potential source;
- wherein a negative differential resistance characteristic of said silicon based NDR FET can be used to shut off a channel of said silicon based NDR FET and reduce static power dissipation during a period when said memory cell is storing the data.
Dependencies are inferred from the claim text.