# US 6,723,657 B2 · Method for fabricating a gate stack in very large scale integrated semiconductor memories

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- Number: US 6,723,657 B2
- Document ID: US6723657B2
- Status: Granted
- Kind: B2
- Application number: 10/159,155
- Filed: 2002-05-31
- Published: 2003-02-20
- Granted: 2004-04-20
- Earliest claimed: 2001-05-31
- Assignees: Infineon Technologies AG
- Inventors: Arkalgud Sitaram
- Web page: https://patentgrep.com/patent/US6723657B2

## CPC

- H10D 30/0225: {using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes}
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for the fabrication of a gate stack, in particular in very large scale integrated semiconductor memories, uses a combination of a damascene process and a CMP process to produce a gate stack which includes a polysilicon section, a silicide section and a covering-layer section thereabove. The gate stack can be fabricated by using conventional materials, has a very low sheet resistance of <1 ohm/unit area and may carry self-aligning contact sections.

## Claims

### Claim 1

A method for fabricating a gate stack above a substrate section covered by a gate oxide layer, in very large scale integrated semiconductor memories, which comprises the following steps:
a) applying a polysilicon layer above the gate oxide layer;
b) applying a silicon nitride layer above the polysilicon layer as a mask layer for a subsequent damascene process;
c) selectively etching an opening, with a side wall and a base, into the silicon nitride layer, down to the polysilicon layer, in the substrate section;
d) covering the silicon nitride layer, including the side wall and the base of the opening, with a Ti or Co layer;
e) converting the Ti or Co at the base of the opening into a silicide section through a conditioning process;
f) removing unsilicided Ti or Co;
g) forming a covering layer entirely over the substrate section, covering the silicon nitride layer and filling the opening above the silicide section;
h) removing the covering layer down to the silicon nitride layer, while retaining the covering layer in the opening;
i) selectively etching the silicon nitride layer down to the polysilicon layer, leaving a gate stack formed of TiSi2 or CoSi2 and a section of the covering layer remaining above the TiSi2 or CoSi2, in the opening;
j) selectively etching the polysilicon layer down to the gate oxide, with the gate stack functioning as a hard mask; and
k) applying a spacer wall around a periphery of the gate stack.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the covering layer formed in step g) is an oxide layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the covering layer formed in step g) is a silicon nitride layer.

### Claim 4 (depends on 1)

The method according to claim 1, which further comprises carrying out the step of removing the covering layer in step h) by a CMP process.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the selective etching step in step i) is a wet-etching process.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the spacer wall applied in step k) is a nitride spacer wall.

### Claim 7 (depends on 1)

The method according to claim 1, which further comprises carrying out the conditioning step e) in a furnace.

### Claim 8 (depends on 1)

The method according to claim 1, which further comprises carrying out a step i′) between the step i) and the step j), and performing the step i′) by forming a spacer wall to protect the silicide against subsequent processes carried out on the gate stack.

### Claim 9 (depends on 8)

The method according to claim 8, which further comprises removing the spacer wall protecting the silicide before the step j).