# US 6,723,623 B1 · Methods of forming implant regions relative to transistor gates

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- Number: US 6,723,623 B1
- Document ID: US6723623B1
- Status: Granted
- Kind: B1
- Application number: 10/326,725
- Filed: 2002-12-20
- Granted: 2004-04-20
- Earliest claimed: 2002-12-20
- Assignees: Micron Technology, Inc.
- Inventors: Phong N. Nguyen
- Web page: https://patentgrep.com/patent/US6723623B1

## CPC

- H10B 12/05: {Making the transistor}
- H10B 12/485: {Bit line contacts}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 41/30: characterised by the memory core region
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopent is implanted through the conductive material to form at least one implant region between and/or beneath the partially formed transistor gates, and subsequently the conductive material is removed from between the gates. The gates can be incorporated into various semiconductor assemblies, including, for example, DRAM assemblies.

## Claims

### Claim 1

A method of forming conductively-doped regions relative to a pair of adjacent transistor gates, comprising:
partially forming a pair of adjacent transistor gates over a semiconductor substrate, the partially-formed transistor gates having a layer of conductive material from the gate extending between them and joining the gates;
forming at least one conductively-doped region between the partially-formed adjacent transistor gates; and
after forming the at least one conductively-doped region, removing the layer of conductive material from between the adjacent transistor gates.

### Claim 2 (depends on 1)

The method of claim 1 wherein at least one conductively-doped region includes a pair of regions extending to under the partially-formed adjacent transistor gates.

### Claim 3 (depends on 1)

The method of claim 1 wherein the conductive material consists of conductively doped silicon.

### Claim 4 (depends on 1)

The method of claim 1 wherein the conductive material consists of conductively doped silicon and has a thickness of from about 100 Å to about 400 Å.

### Claim 5 (depends on 1)

The method of claim 1 wherein the at least one conductively-doped region comprises an LDD region.

### Claim 6 (depends on 1)

The method of claim 1 wherein the at least one conductively-doped region includes a pair of pocket implant regions, and further comprising forming a heavily-doped source/drain region extending between the pocket implant regions and shared by the adjacent transistor gates.

### Claim 7 (depends on 1)

The method of claim 1 wherein the at least one conductively-doped region includes a pair of pocket implant regions and an LDD region.

### Claim 8 (depends on 1)

The method of claim 1 further comprising incorporating the adjacent transistor gates into a pair of adjacent DRAM cells, the adjacent cells sharing a bitline connection.

### Claim 9 (depends on 1)

The method of claim 1 wherein the partially formed transistor gates have sidewall edges, and further comprising forming electrically insulative sidewall spacers along the sidewall edges of the partially formed transistor gates.

### Claim 10

A method of forming angled implants relative to a pair of adjacent transistor gates, comprising:
forming a gate stack over a substrate, the gate stack comprising a layer of electrically conductive material;
etching only partially through the layer of electrically conductive material to leave an unetched remaining portion of the electrically conductive material and to partially form a pair of adjacent transistor gates from the gate stack;
implanting at least one dopant at an angle other than 0° relative to vertical to form pocket implant regions under the partially formed adjacent transistor gates; and
after the implanting, etching through the remaining portion of the electrically conductive material and completing formation of the pair of adjacent transistor gates.

### Claim 11 (depends on 10)

The method of claim 10 wherein the partially formed transistor gates have sidewall edges, and further comprising forming electrically insulative sidewall spacers along the sidewall edges of partially formed transistor gates.

### Claim 12 (depends on 10)

The method of claim 10 further comprising forming a heavily-doped source/drain region shared by the adjacent transistor gates; the forming the heavily-doped source/drain region occurring before the formation of the pocket regions.

### Claim 13 (depends on 10)

The method of claim 10 further comprising forming a heavily-doped source/drain region shared by the adjacent transistor gates; the forming the heavily-doped source/drain region occurring after the formation of the pocket regions.

### Claim 14 (depends on 13)

The method of claim 13 wherein the forming the heavily-doped source/drain region occurs prior to the etching through the remaining portion of the electrically conductive material.

### Claim 15 (depends on 13)

The method of claim 13 wherein the forming the heavily-doped source/drain region occurs after the etching through the remaining portion of the electrically conductive material.

### Claim 16 (depends on 10)

The method of claim 10 wherein the layer of electrically conductive material comprises conductively-doped silicon.

### Claim 17 (depends on 10)

The method of claim 10 wherein the layer of electrically conductive material consists of conductively-doped silicon.

### Claim 18 (depends on 17)

The method of claim 17 wherein the layer of electrically conductive material is a first layer of conductive material; and wherein the gate stack comprises:
a pad oxide layer between the first layer of conductive material and the substrate;
at least one more layer of conductive material over the first layer of conductive material; and
an insulative layer over the at least one more layer of conductive material.

### Claim 19 (depends on 18)

The method of claim 18 wherein the at least one more layer of electrically conductive material comprises a layer of tungsten over a layer of tungsten nitride.

### Claim 20 (depends on 18)

The method of claim 18 wherein the insulative layer comprises silicon nitride.

### Claim 21

A method of forming angled implants relative to a pair of adjacent transistor gates, comprising:
forming a gate stack over a substrate, the gate stack comprising a first layer;
etching only partially through the first layer to leave an unetched remaining portion of the first layer and to partially form a pair of adjacent transistor gates from the gate stack, the partially formed transistor gates have sidewall edges;
forming a second layer along the sidewall edges of the partially formed pair of adjacent transistor gates;
after forming the second layer, implanting at least one dopant at an angle other than 0° relative to vertical to form pocket implant regions under the partially formed adjacent transistor gates; and
after the implanting, etching through the remaining portion of the first layer and completing formation of the pair of adjacent transistor gates.

### Claim 22 (depends on 21)

The method of claim 21 further comprising anisotropically etching the second layer prior to the etching of the remaining portion of the first layer.

### Claim 23 (depends on 21)

The method of claim 21 wherein the first layer is an electrically conductive material.

### Claim 24 (depends on 21)

The method of claim 21 wherein the first layer consists of conductively doped silicon.

### Claim 25 (depends on 21)

The method of claim 21 wherein the second layer is an electrically insulated material.

### Claim 26 (depends on 21)

The method of claim 21 wherein the second layer consists of silicon nitride.

### Claim 27 (depends on 21)

The method of claim 21 wherein the first layer is an electrically conductive material and the second layer is an electrically insulative material.

### Claim 28 (depends on 21)

The method of claim 21 wherein the first layer consists of conductively doped silicon and the second layer consists of silicon nitride.

### Claim 29

A method of forming a DRAM assembly, comprising:
forming a gate stack over a substrate, the gate stack comprising a layer of electrically conductive material;
etching only partially through the layer of electrically conductive material to leave an unetched remaining portion of the electrically conductive material and to partially form a pair of adjacent transistor gates from the gate stack; one of the adjacent transistor gates ultimately being incorporated into a first DRAM cell and the other of the adjacent transistor gates ultimately being incorporated into a second DRAM cell;
forming pocket implant regions under the partially formed transistor gates;
after the forming the pocket implant regions, etching through the remaining portion of the electrically conductive material, and completing formation of the pair of adjacent transistor gates;
forming a heavily doped source/drain region shared by the adjacent transistor gates;
forming first and second data storage devices for the first and second DRAM cells, respectively; and
forming a bitline contact in electrical with the source/drain region.

### Claim 30 (depends on 29)

The method of claim 29 wherein the data storage devices are capacitors.

### Claim 31 (depends on 29)

The method of claim 29 wherein the forming the heavily-doped source/drain region occurs before the formation of the pocket regions.

### Claim 32 (depends on 29)

The method of claim 29 wherein the forming the heavily-doped source/drain region occurs after the formation of the pocket regions.

### Claim 33 (depends on 32)

The method of claim 32 wherein the forming the heavily-doped source/drain region occurs prior to the etching through the remaining portion of the electrically conductive material.

### Claim 34 (depends on 32)

The method of claim 32 wherein the forming the heavily-doped source/drain region occurs after the etching through the remaining portion of the electrically conductive material.

### Claim 35 (depends on 29)

The method of claim 29 wherein the layer of electrically conductive material consists of conductively-doped silicon.

### Claim 36 (depends on 35)

The method of claim 35 wherein the layer of electrically conductive material is a first layer of conductive material; and wherein the gate stack comprises:
a pad oxide layer between the first layer of conductive material and the substrate;
at least one more layer of conductive material over the first layer of conductive material; and
an insulative layer over the at least one more layer of conductive material.

### Claim 37 (depends on 36)

The method of claim 36 wherein the at least one more layer of electrically conductive material comprises a layer of tungsten over a layer of tungsten nitride.

### Claim 38 (depends on 36)

The method of claim 36 wherein the insulative layer comprises silicon nitride.

### Claim 39

A method of forming a pair of adjacent memory cells sharing a common bitline, comprising:
forming a gate stack over a substrate, the gate stack comprising a layer of electrically conductive material;
etching only partially through the layer of electrically conductive material to leave an unetched remaining portion of the electrically conductive material and to partially form a pair of adjacent transistor gates from the gate stack; one of the adjacent transistor gates ultimately being incorporated into a first transistor and the other of the adjacent transistor gates ultimately being incorporated into a second transistor;
defining three source/drain region locations relative to the partially formed transistor gates, a first of the source/drain region locations being associated with only the first transistor; a second of the source/drain region locations being shared by the first and second transistors, and a third of the source/drain region locations being associated with only the second transistor;
forming a mask over the first and third source/drain region locations;
while the mask is over the first and third source/drain region locations, implanting at least one dopant at an angle other than 0° relative to vertical to form pocket implant regions under the partially formed transistor gates;
after the implanting, removing the mask, etching through the remaining portion of the electrically conductive material, and completing formation of the pair of adjacent transistor gates;
forming first, second and third heavily doped source/drain regions at the first, second and third source/drain region locations, respectively;
forming first and second data storage devices in electrical connection with the first and third source/drain regions, respectively; and
forming a bitline contact in electrical with the second source/drain region.

### Claim 40 (depends on 39)

The method of claim 39 further comprising, while the mask is over the first and third source/drain region locations, implanting at least one dopant to form an LDD region between the partially formed transistor gates.

### Claim 41 (depends on 39)

The method of claim 39 wherein the data storage devices are capacitors.

### Claim 42 (depends on 39)

The method of claim 39 wherein the forming the heavily-doped source/drain regions occurs before the formation of the pocket regions.

### Claim 43 (depends on 39)

The method of claim 39 wherein the forming the heavily-doped source/drain regions occurs after the formation of the pocket regions.

### Claim 44 (depends on 43)

The method of claim 43 wherein the forming the heavily-doped source/drain regions occurs prior to the etching through the remaining portion of the electrically conductive material.

### Claim 45 (depends on 43)

The method of claim 43 wherein the forming the heavily-doped source/drain regions occurs after the etching through the remaining portion of the electrically conductive material.

### Claim 46 (depends on 39)

The method of claim 39 wherein the layer of electrically conductive material comprises conductively-doped silicon.

### Claim 47 (depends on 39)

The method of claim 39 wherein the layer of electrically conductive material comprises conductively-doped silicon.

### Claim 48 (depends on 47)

The method of claim 47 wherein the layer of electrically conductive material is a first layer of conductive material; and wherein the gate stack comprises:
a pad oxide layer between the first layer of conductive material and the substrate;
at least one more layer of conductive material over the first layer of conductive material; and
an insulative layer over the at least one more layer of conductive material.

### Claim 49 (depends on 48)

The method of claim 48 wherein the at least one more layer of electrically conductive material comprises a layer of tungsten over a layer of tungsten nitride.

### Claim 50 (depends on 48)

The method of claim 48 wherein the insulative layer comprises silicon nitride.

### Claim 51

A method of forming an electronic system, comprising:
forming a gate stack over a substrate, the gate stack comprising a layer of electrically conductive material;
etching only partially through the layer of electrically conductive material to leave an unetched remaining portion of the electrically conductive material and partially forming transistor gates from the gate stack; at least some of the partially formed transistor gates being paired adjacent transistor gates;
forming pocket implant regions under at least some of the partially formed paired adjacent transistor gates;
after the forming the pocket implants, etching through the remaining portion of the electrically conductive material, and completing formation of the transistor gates;
forming source/drain regions proximate the transistor gates, some of the source/drain regions being shared by paired adjacent transistor gates;
forming data storage devices in electrical connection with at least some of the source/drain regions;
forming bitline contacts in electrical with at least some of the shared source/drain regions; the data storage devices, paired adjacent transistors and bitline contacts being incorporated into an array of memory cells;
forming addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and
forming a read circuit coupled to the array of memory cells for reading data from memory cells in the array of memory cells.

### Claim 52 (depends on 51)

The method of claim 51 wherein the memory cells are incorporated into devices selected from the group consisting of SDRAM, DDR SDRAM, SLDRAM, Direct RDRAM, SRAM, VRAM, EEPROM, and Flash memories.

### Claim 53 (depends on 51)

The method of claim 51 wherein the data storage devices are capacitors.

### Claim 54 (depends on 51)

The method of claim 51 wherein the forming the heavily-doped source/drain regions occurs before the formation of the pocket regions.

### Claim 55 (depends on 51)

The method of claim 51 wherein the forming the heavily-doped source/drain regions occurs after the formation of the pocket regions.

### Claim 56 (depends on 55)

The method of claim 55 wherein the forming the heavily-doped source/drain regions occurs prior to the etching through the remaining portion of the electrically conductive material.

### Claim 57 (depends on 55)

The method of claim 55 wherein the forming the heavily-doped source/drain regions occurs after the etching through the remaining portion of the electrically conductive material.

### Claim 58 (depends on 51)

The method of claim 51 wherein the layer of electrically conductive material consists of conductively doped silicon.

### Claim 59 (depends on 58)

The method of claim 58 wherein the layer of electrically conductive material is a first layer of conductive material; and wherein the gate stack comprises:
a pad oxide layer between the first layer of conductive material and the substrate;
at least one more layer of conductive material over the first layer of conductive material; and
an insulative layer over the at least one more layer of conductive material.

### Claim 60 (depends on 59)

The method of claim 59 wherein the at least one more layer of electrically conductive material comprises a layer of tungsten over a layer of tungsten nitride.

### Claim 61 (depends on 59)

The method of claim 59 wherein the insulative layer comprises silicon nitride.